吃瓜tv · Signal integrity & fabrication
PCB Impedance: Calculate, Design & Control
PCB trace impedance depends on the conductor geometry, dielectric and reference planes. Controlled impedance in a PCB means designing and manufacturing those features to meet an agreed target, then checking the defined test structures.
Start with a calculation. Finish with a stackup, net-class requirements and a test plan your fabricator can use.
Open the impedance calculator Send a stackup for review
PCB Impedance Calculator
Enter the finished geometry in mm or mil. Calculate single-ended or differential impedance, or solve for a starting width at a fixed gap. The model explains unsupported inputs instead of silently substituting values.
Controlled Impedance Calculator
Before you use a result: a nominal impedance estimate does not guarantee a fabricated tolerance. Solder mask, trapezoidal etching, glass weave, copper roughness, material dispersion and transitions need additional modeling or measurement.
What is PCB impedance—and what is controlled impedance?
In this guide, PCB impedance means the characteristic impedance of a transmission line: the voltage-to-current ratio of a traveling wave. It is different from the copper trace’s DC resistance and from the input impedance of a complete terminated circuit.
For a low-loss line, the starting relationship is:
Z? ≈ √(L′ / C′)
L′ and C′ are inductance and capacitance per unit length. In the general lossy case, Z? = √[(R′ + jωL′) / (G′ + jωC′)]. These per-length quantities depend on the physical stackup and frequency.
When does it matter?
Consider the signal edge rate and the route delay, not only the clock frequency. A physically long interconnect relative to the transition time can behave as a transmission line even when the repetition rate seems modest.
Typical starting targets include 50 Ω single-ended and 90 or 100 Ω differential, but the interface specification, device design guide and channel budget set the requirement. They are not universal defaults.
Review the broader controlled-impedance background for context, and use this page for geometry calculations and a fabrication-ready requirement list.
Choose the right transmission-line structure
| Structure | Use it when | Important limitation |
|---|---|---|
| Surface microstrip | A surface trace runs above one continuous reference plane. | This calculator omits solder mask and nearby same-layer copper. |
| Centered stripline | A trace is centered between two reference planes in homogeneous dielectric. | An asymmetric or mixed-Dk stackup needs a different model. |
| Edge-coupled differential pair | Two traces carry the differential signal; enter the edge-to-edge spacing. | Differential impedance is 2 × odd-mode impedance, not automatically 2 × isolated-trace impedance. |
| Grounded coplanar | Side grounds and a continuous backside plane surround a surface trace. | The included comparison uses zero copper thickness and ideal lateral grounds; it does not model a via fence. |
Agree the dielectric build first. Use multilayer stackup planning for layer organization and RF PCB material selection when laminate and loss requirements dominate.
What changes the impedance?
| Change | Usual effect | What to check before changing layout |
|---|---|---|
| Increase trace width | Lower impedance | Pad neck-downs, spacing rules and the fabricator’s etch compensation. |
| Increase dielectric spacing | Higher impedance | Pressed dielectric thickness and the actual reference layer. |
| Increase Dk | Lower impedance | Use the appropriate design Dk, frequency and test/model basis. |
| Reduce differential edge gap | Lower differential impedance | Coupling, routing clearance and geometry-dependent model limits. |
| Increase finished copper thickness | Usually lower impedance in these models | Base foil and finished plated thickness are different quantities. |
FR-4 is a material family, not one fixed Dk. Do not substitute a laminate’s process Dk for design Dk without understanding the supplier’s test method. Rogers explains this distinction in its .
Controlled-impedance PCB design tips
- Freeze the reference geometry early. Identify each signal layer and reference plane before treating a width as final. Ask whether the quoted dielectric is a finished pressed value.
- Keep the reference continuous. Plane splits, voids and changes of reference can interrupt the return path. Layer transitions need a deliberate return connection; stitching details depend on the planes and channel.
- Define each net class. Record single-ended or differential target, tolerance, signal layer, reference layers and any allowed geometry changes.
- Control local discontinuities. Pads, connectors, vias, neck-downs and stubs need attention even if the long straight trace calculates correctly. Length matching alone cannot fix a poor transition.
- Model the real cross-section. Include mask and conductor shape when they matter. A nearby copper pour makes a surface trace different from an isolated microstrip.
- Use matched assumptions across tools. Compare W, T, H/B, Dk basis, gap and coating before deciding that two calculators disagree.
- Separate impedance from loss. A matched trace may still exceed insertion-loss or timing budgets. Use high-frequency loss and phase guidance for that next task.
- Approve adjustments before release. Let the fabricator propose stackup and width changes, but record approval rather than silently changing critical routing.
For device-specific layout constraints, use the applicable manufacturer guide; is a useful general reference.
How controlled impedance is verified
Time-domain reflectometry (TDR) relates voltage reflections to impedance changes along a test structure. A representative coupon can check fabrication consistency for an agreed layer and geometry. It does not, by itself, validate every connector or via in the complete signal channel. If an unused via barrel limits the channel, review the backdrill residual-stub and depth envelope with the actual stackup.
| Stage | Agree or record |
|---|---|
| Before fabrication | Approved stackup, finished geometry, target/tolerance, net classes, coupon structures and sampling scope. |
| During evaluation | Test method, fixture/probe setup, reference calibration and the evaluation region. Launch effects should not be confused with the controlled test region. |
| At release | Measured result against the agreed limits, coupon/lot identity, exceptions and the required report. |
A request for 50 Ω ±10% describes a 45–55 Ω acceptance interval only when that requirement has been agreed. The calculator’s percent deviation is a mathematical comparison, not a capability promise. See fabrication capabilities and quality assurance documentation when preparing supplier review.
笔辞濒补谤’蝉 explains the relationship between modeling, coupons and manufacturing characterization.
Understand the calculator’s models
The supported equations are fast screening tools. They intentionally have narrower operating ranges than a full field solver. An input being inside a screening range is not a stated accuracy guarantee.
| Model | Equation / scope |
|---|---|
| Microstrip | Z? ≈ 87 / √(Dk + 1.41) × ln[5.98H / (0.8W + T)]. Screening: W/H 0.1–2, T/H ≤0.25; Dk 2–10. |
| Centered stripline | Z? ≈ 60 / √Dk × ln[1.9B / (0.8W + T)]. Screening: W/B 0.05–0.6, T/B ≤0.1; Dk 2–10. |
| Differential microstrip | Zdiff ≈ 2Zisolated × [1 ? 0.48 exp(?0.96S/H)]. Empirical edge-coupling approximation; S/H 0.1–3. |
| Differential centered stripline | Zdiff ≈ 2Zisolated × [1 ? 0.347 exp(?2.9S/Hc)], with Hc = (B ? T)/2. Centered pair only; S/Hc 0.1–3. |
| Grounded coplanar | Quasi-static conformal mapping with ideal side/backside grounds; T must explicitly be zero. Screening: W/H 0.1–5 and gap/H 0.1–3. |
The inverse width calculation uses the same model and the same fixed edge gap as the forward calculation. Delay is an additional approximation based on effective permittivity; frequency-dependent dispersion is not modeled.
Single-line equations and their caveats are discussed in . The describes the underlying analytical approach. Pair approximations follow the geometry in . Tight-coupled, coated, asymmetric, mixed-material or high-precision structures should proceed to a suitable field solver and measurement.
Turn a calculation into useful fabrication notes
| Send this | Example or clarification |
|---|---|
| Stackup revision | Material and construction, signal/reference layers, finished dielectric thickness and copper. |
| Impedance table | Net class; layer; single-ended/differential; target; agreed tolerance; reference geometry. |
| Geometry and constraints | Trace width, edge gap, mask condition, restricted areas and whether CAM changes may be proposed. |
| Material basis | Named grade if fixed; design Dk and frequency/method basis where available. Unknowns can be marked for review. |
| Test and acceptance scope | Coupon types, reporting, sampling, acceptance window and any channel-level testing outside bare-board TDR. |
| Commercial scope | Board dimensions, quantity, lead-time requirement, special processing and expected documentation. |
What affects controlled-impedance PCB cost?
Laminate, stackup, finished geometry, tolerance and inspection scope affect the fabrication route. A tighter requested band can require additional modeling or process review. There is no reliable universal “impedance surcharge” multiplier; request pricing against the agreed scope.
Use the PCB manufacturing page for a broader fabrication estimate. For an exact review, attach the calculation download and your released files. No calculator on this page uploads Gerber data or approves manufacturability.
Request a stackup & impedance reviewPCB impedance questions
Is a 50 Ω trace a 50 Ω resistor?
No. The value is the characteristic impedance of the transmission line, not its end-to-end DC resistance. A multimeter resistance reading does not validate controlled impedance.
What width gives 50 Ω on FR-4?
There is no single width. The reference-plane spacing, finished copper, design Dk and surrounding geometry must be specified first. Use the calculator to explore a defined cross-section.
Does trace length change characteristic impedance?
For a uniform line with the same cross-section, nominal characteristic impedance does not depend on length. Length does affect propagation delay, loss and the input response of a terminated channel.
Can I use total PCB thickness as H?
Only when that thickness actually represents the dielectric spacing to the reference plane for the modeled trace. On a multilayer board, H is generally one part of the stackup.
Why is the stripline input called B?
B is the complete spacing between the two reference planes. The included stripline model requires a centered trace and homogeneous dielectric; it cannot solve an arbitrary top/bottom height ratio.
Is 100 Ω differential the same as two 50 Ω isolated traces?
Not generally. Coupling changes the odd-mode impedance. The differential impedance is twice the odd-mode value, while an isolated-trace estimate ignores the neighboring signal conductor.
Does solder mask matter?
It can change the effective dielectric environment of a surface trace. The included surface models omit it. Use a coated cross-section model where the required accuracy calls for it.
Why does my field solver give another number?
Check that both tools use the same copper cross-section, plane distances, dielectric values, coatings and neighboring copper. Closed-form screening approximations and field solvers do not have the same assumptions.
Can the tool guarantee ±5% or ±10%?
No. It reports nominal values and an optional input-corner envelope. A production tolerance needs an agreed stackup, process, coupon and evaluation method.
Should I select material by Dk alone?
No. Frequency dependence, loss, roughness, construction, availability and manufacturing requirements also matter. Use the appropriate supplier data and a consistent modeling basis.
Can I send incomplete specifications?
Yes. Identify the target interface and the unresolved stackup or material questions. Submit available files for engineering review rather than guessing a material or claiming the calculation is final.