吃瓜tv 路 ANALOG DESIGN REVIEW
ADC Input Settling PCB Review: Source Impedance and Sampling Time
A correct DC voltage at an ADC pin does not prove that its internal sampling capacitor reaches that voltage before conversion. For a SAR ADC, review the source impedance, acquisition window and worst input step together. Then check whether the layout and driver preserve the result.
This guide develops a simple settling calculation and a board-level diagnostic sequence. It applies to a simplified SAR input model; use the selected converter’s datasheet for its actual timing, input network and guaranteed performance.
Find the acquisition window before calculating an RC time
A sampling cycle contains several different intervals. During acquisition, the input must charge the internal sampling network sufficiently close to the intended voltage. During conversion, the converter determines the digital result. Data transfer, multiplexer switching and idle time may occupy other intervals, and some architectures overlap certain activities. The complete sample period is therefore not automatically available for acquisition.
For example, a 100 ksample/s rate gives a 10 碌s sample period. If the selected timing mode permits only 1 碌s of acquisition, a calculation based on 10 碌s is optimistic by a factor of ten. Lowering the rate helps only if it actually extends acquisition or allows the relevant external circuitry to recover. Check the clock and control timing rather than inferring the result from a throughput setting.
identifies the sample capacitor, source resistance and internal switching impedance as relevant inputs. Their values and limitations are device-dependent. In an MCU, also check which sample-time register applies to the channel, what changes after a channel switch, and whether firmware reconfigures the ADC clock.
A useful design-review record lists the ADC part number and revision, resolution, full-scale span, acquisition duration and worst preceding-channel voltage. If one of these is unknown, mark it as an open requirement. 鈥淭he ADC is slow鈥� is not enough information to approve its input circuit.
Calculate a screening limit for a first-order model
Suppose an ideal source drives a capacitor through a total resistance R. After an initial voltage step 螖V, the remaining error in this first-order model is 螖V 脳 exp(鈭抰/RC). R includes the resistances represented in the model, not just a visible series resistor. For a divider, determine its Thevenin resistance; two divider resistors contribute their parallel resistance when the source is treated as ideal for this calculation.
t 鈮� RC 脳 ln(螖V / Vallowed)
For a full-scale step and a half-LSB settling allowance in an ideal N-bit converter, Vallowed = VFS/2N+1. The minimum screening time becomes (N + 1) 脳 ln(2) 脳 RC. This allocates a half LSB to settling only; it does not include offset, gain error, reference error, noise or integral nonlinearity. A real system may allocate less than half an LSB to this one contribution.
Take an illustrative total R of 5 k惟 and C of 20 pF. Their product is 100 ns. For 12 bits and a full-scale step, the ideal time is about 901 ns. At only 500 ns, the remaining error is exp(鈭�5), approximately 0.674% of full scale, or 27.6 LSB for a 12-bit converter. At 1 碌s, the model predicts approximately 0.186 LSB. These numbers are calculated examples, not specifications for a particular ADC.
| Resolution | Time for a full-scale step to half an LSB | At RC = 100 ns |
|---|---|---|
| 10 bits | 7.625 脳 RC | 762.5 ns |
| 12 bits | 9.011 脳 RC | 901.1 ns |
| 14 bits | 10.397 脳 RC | 1.040 碌s |
| 16 bits | 11.784 脳 RC | 1.178 碌s |
The model is useful for rejecting an obviously inadequate acquisition window. It does not approve a complete circuit. Input-switch resistance can vary with voltage, the sampling network may redistribute charge, and an amplifier introduces bandwidth, slew-rate and stability limits. A larger capacitor added at the pin creates a different dynamic network; it should not simply be substituted for the internal sampling capacitance in this equation.
Identify what the ADC is asking the source to drive
A sensor may appear low impedance at DC yet respond poorly to short charging pulses. Include its output stage, cable, protection network, divider, filter and multiplexer in the signal path. The ADC input should be assessed at the conversion conditions, not only with a high-impedance meter. A circuit that passes a slow voltage sweep may still fail when the channel sequence alternates between opposite ends of the input range.
demonstrates the importance of the acquisition behavior of a specific unbuffered converter. Treat its component choices as an example for that circuit. A general review should compare the selected ADC input model with the actual source and operating mode before choosing a buffer or reservoir capacitor.
A driver amplifier needs adequate settling for the required step, output swing and load. Unity-gain bandwidth alone is not a settling guarantee. Check its stability with the proposed capacitance, output recovery, noise and operating supply range. A series isolation resistor can help an amplifier drive capacitance but also introduces resistance into the charging path. Select the driver and filter together, then verify their combined response.
For channels that also require gain and offset, use the sensor-to-ADC range mapping guide. That establishes the signal span. The review here begins where a correct span still has to settle in the available time.
Translate the circuit into a controlled analog path
Place the selected input-filter components so that the intended network exists at the ADC pins, with a short and understandable return path. A capacitor located beyond a long trace or shared return is not electrically identical to the one in a compact reference circuit. Keep the sensitive input route away from clock edges, switching-power nodes and heavily loaded digital outputs.
Review the return path with the signal route. Do not cut a ground plane merely because a net is labelled analog; a poorly placed split can force current to detour beneath sensitive circuitry. Follow the converter manufacturer’s grounding arrangement and place noisy functions so their return currents have a suitable path. Treat differential inputs as a pair with the required common-mode range, rather than assuming that subtracting two readings removes every coupling mechanism.
The reference input deserves a separate check. explains that a SAR reference can have dynamic charge demands during conversion. A stable signal input cannot compensate for a reference that moves during a decision. Check the specified reference driver, storage capacitor, placement and return connection. Do not use a generic capacitor value from another converter.
Reserve practical measurement access without making the test point a major capacitive stub. Include probe loading in the test plan, especially for high-impedance nodes. When comparing a simulated waveform with a bench waveform, record the probe and fixture arrangement; the measurement itself can change the network being investigated.
Diagnose settling with controlled changes
Use a repeatable source and save raw conversion results. Test a fixed input first, then alternate channels or input levels to create the largest credible step. Compare the first retained sample with subsequent samples at the same intended voltage. Averaging may reduce random noise while preserving a systematic first-sample bias, so review the sequence before applying an average.
- Lengthen only the acquisition interval. Keep the source, channel order and other settings fixed. A reduced error supports a settling hypothesis but does not uniquely identify the responsible component.
- Change the preceding channel. Compare a small step with the largest expected step. Note both the direction and magnitude of any first-sample error.
- Compare a known lower-impedance source. Use an appropriate test configuration, not an improvised short across protection or a live sensor output. A changed result helps locate a source-drive limitation.
- Observe the reference and supplies. A conversion-correlated disturbance can resemble an input problem. Use the manufacturer’s measurement guidance and suitable probes.
- Repeat at the specified operating extremes. Include temperature, supply and component tolerances in the final qualification scope, rather than approving from one typical board at room temperature.
A discarded first conversion can be legitimate if the device documentation and system timing support it. It is not a universal repair. Confirm which sample corresponds to which channel, whether the capacitor is reacquired, and whether losing a sample is acceptable to the application. Some converters have digital pipeline or filter latency that must be handled separately from analog settling.
Why can the DMM reading be correct while ADC samples are wrong?
A DMM commonly observes a comparatively slow, lightly loaded voltage. The ADC can impose brief sampling demands and retain charge from a previous level. A correct average pin voltage does not establish the voltage at the internal hold capacitor when conversion begins.
Does lowering the sample rate always fix the problem?
No. It must extend the relevant acquisition or recovery interval. Some modes keep acquisition fixed while adding idle time elsewhere. Check the timing diagram and the actual configuration.
Should every ADC input use a buffer?
No. A suitable source may drive the selected ADC directly. A buffer adds its own noise, offset, power and stability requirements; use it when the interface analysis justifies it.
Make the design decision reproducible
For manufacturing, release the ADC and driver manufacturer part numbers, approved alternatives, filter values, board revision and placement data together. If substitutions are allowed, define which electrical characteristics must be checked before acceptance. A similar pinout is insufficient when a different input architecture or amplifier response changes the acquisition requirement.
Include programming and test instructions if acquisition timing is firmware-dependent. A production test that checks only one DC point may miss an error that appears after channel switching. State the intended channel sequence, allowed error, settling interval and reference equipment in the test procedure, so the assembly team can review the required coverage.
The PCB design review provides the wider layout context. When the circuit and evidence are ready, a PCB assembly enquiry should include the controlled files and test scope. 吃瓜tv can review the requested build; the analytical example on this page is not a qualification of an unreviewed design.
Technical basis
Sources: , , and . The RC example and figures are original explanatory calculations, not measured ADC performance. Reviewed October 10, 2026.