4-Layer PCB Stackup
Define copper, core and bonding regions together. Check the thickness sum, then agree the actual material schedule with fabrication.
Open the thickness worksheet 鈫� 路 4-layer fabrication & quotation
Layer-role concept 路 not a released stackup. Physical spacing is illustrative.
4-layer construction, in one view
Enter a proposed construction. Check its arithmetic and take the open questions to fabrication.
A matching worksheet is available from your previous page.
Two 1.6 mm boards can need different trace widths
The four-layer count tells you how many copper layers exist, not the spacing relevant to a surface transmission line. In a conventional foil construction, changing the central core can alter overall thickness substantially while leaving the outer signal-to-reference gaps nearly unchanged. Changing the outer bonding regions can alter impedance even when a compensating core change keeps the same finished thickness.
Compare concept A with 0.10 mm outer dielectric gaps and concept B with 0.20 mm gaps. Assume the same dielectric model and ignore conductor thickness for this first comparison. If the width-to-height ratio is held constant, the ideal microstrip impedance remains approximately constant. Concept B therefore requires approximately twice the width. This scaling result is useful for understanding why a copied width can fail; it is not a fabrication width prescription.
The physical conductor is not infinitely thin. Finished copper, etch taper, solder mask and nearby coplanar ground change the result. A fabricator's solver table should list those assumptions with the width. Ask whether a supplied value is the CAD artwork width, a finished top width, an effective trapezoidal width or an adjusted manufacturing value. An unqualified number called trace width can refer to several different stages.
This distinction matters around fine-pitch devices. A wide nominal impedance line may not fit between pads, so a short neck-down may be necessary. Document its length and geometry, and evaluate its effect separately instead of pretending the entire route has the nominal cross-section.
Make the 50-ohm requirement belong to a net class
Fifty ohms is a common reference impedance, but it is not a universal design requirement for every signal. The interface specification and device documentation determine the target, termination and allowable channel behavior. A differential impedance requirement also needs pair spacing and an appropriate coupled model; it cannot be specified by doubling a single-ended calculator value without checking coupling.
Create one row per controlled class: interface name, target impedance, tolerance, signal layer, reference layer, finished copper and geometry. If top and bottom constructions differ, give them separate rows. State whether a grounded coplanar structure is intended and include its gap to ground. A bottom route above a segmented power plane needs a return-path review even if its local cross-section produces the requested nominal impedance.
For a four-layer controller, a signal-ground-ground-signal arrangement can give both routing surfaces a ground reference, provided the planes remain continuous. Power then needs deliberate distribution on the available routing copper. A signal-ground-power-signal arrangement frees a plane for power but requires careful handling of bottom-layer returns and rail splits. These are architectural tradeoffs, not a contest with one universally correct stack.
Specify the acceptance method separately from the design target. A coupon result samples an agreed structure under an agreed test setup. It does not demonstrate that every connector launch, neck-down and via transition on the board has constant impedance. Keep geometry verification and manufactured coupon acceptance as related but distinct checks.
Use sensitivity before choosing tighter tolerances
A tolerance study is more useful than displaying an excessive number of digits from a nominal calculator. Start with the accepted nominal construction, then vary dielectric height, conductor width and the chosen material parameter within defensible ranges. Change one variable at a time first so the team sees which parameter dominates. Next examine realistic combinations; manufacturing variables may be correlated and should not automatically be treated as independent worst cases.
For an illustrative zero-thickness microstrip, take relative permittivity 4 and width-to-height ratio 2. A common quasi-static approximation gives effective permittivity about 3.07 and characteristic impedance about 51 ohms. Doubling both width and height leaves that ideal result unchanged. Holding width fixed while increasing height does not. The example explains geometry sensitivity; solder mask, finite copper and actual material dispersion are deliberately excluded.
If the proposed tolerance cannot be achieved without an impractical narrow line, revisit the stackup rather than demanding arbitrary precision from etching. Conversely, do not impose tight overall board thickness solely to control a surface impedance gap when a different dielectric allocation can decouple those constraints. Tell the fabricator which dimension actually controls the circuit.
Record the model name, input units and excluded effects with the result. Where a supplier provides a better validated geometry, replace the illustrative inputs rather than averaging incompatible answers. A numerical disagreement is often an assumptions problem, not proof that one calculator is defective.
Resolve fabrication questions before routing is frozen
Send the desired mechanical thickness and controlled net classes before detailed routing. Request a construction proposal that includes pressed outer gaps, core identity, foil and finished copper. Then check whether the recommended widths fit escapes, connectors and differential-pair corridors. This early exchange is especially useful when a board must mate with an edge connector or fit a thin enclosure.
If a supplier needs to change width after artwork release, ask which nets and regions are affected. A blanket width adjustment may collide with pads, alter pair spacing, or change a tuned RF structure. Define which uniform transmission-line segments may be adjusted and which regions require engineering approval. Preserve the accepted changes in the CAD source, not only in manufacturing files.
The review attachment provided with this article has separate fields for requested and approved geometry, plus the reference plane and mask condition. Use it with the existing four-layer thickness worksheet. It does not perform a new field simulation or automatically send data to a quotation form. Download it, fill the unresolved fields and attach it to a project enquiry.
For purchasing, compare quotations using the same impedance scope and inspection records. A board with ordinary electrical continuity testing is not equivalent to one with the specified impedance coupon and report. An exact quotation should state the accepted construction and what happens if a proposed material is unavailable. This keeps the procurement decision connected to the design that was actually reviewed.
Work through thin and thick four-layer targets
Compare the 0.8, 1.2 and 1.6 mm target examples above by reading the PP entries first, then the central core. A thin finished board need not put each dielectric at one third of the total thickness. Equally, a thick board need not require a very thick outer signal-to-plane gap. The reference candidate can leave a small nominal difference from the target; agree tolerance and pressed values before treating it as a drawing.
Choose the layer roles before accepting an outer-line width. In signal鈥揼round鈥揼round鈥搒ignal, each surface route has a nearby ground reference if the adjacent plane is continuous. In signal鈥揼round鈥損ower鈥搒ignal, the bottom route sees the power structure; review rail splits and how its return transfers at each transition. A single 50-ohm field is not sufficient to specify all nets.
4-layer thickness, core and prepreg examples
Start with the mechanical constraint, then check whether the electrical allocation can fit within it. A connector stack height or enclosure is a target; it does not establish the availability of a particular prepreg construction. In a conventional even-layer foil build, cores and bonding gaps can be counted before the exact materials are chosen. Odd-count examples below are geometry allocations only.
| Target | Core / substrate | Prepreg / bonding region | Calculated total | Difference |
|---|---|---|---|---|
| 0.80 mm | 1 脳 0.356 mm | 2 gaps; each 2 脳 1080, 65% RC | 0.798 mm | -0.002 mm |
| 1.20 mm | 1 脳 0.711 mm | 2 gaps; each 1 脳 7628, 42% RC | 1.199 mm | -0.001 mm |
| 1.60 mm | 1 脳 1.200 mm | 2 gaps; each 1 脳 1652, 50% RC | 1.606 mm | +0.006 mm |
Planning examples: 35 碌m finished surface copper, 18 碌m inner copper, zero separate coating allowance. These are reference candidates, not stocked or released constructions. A difference is not an approved tolerance. The tool can change the target and edit every dielectric row. Values above the FR406 reference core range are nominal design targets.
A digital controller moving from two layers
A four-layer controller can keep two routing surfaces adjacent to reference planes. Signal鈥揼round鈥揼round鈥搒ignal is useful when power can be distributed on the routing surfaces; signal鈥揼round鈥損ower鈥搒ignal instead requires a deliberate bottom-signal reference and decoupling strategy. Neither arrangement removes the need to examine return transitions at connectors and vias.
Check the reference, not just the layer number
| Review | What to record |
|---|---|
| Reference for each critical layer | Identify the continuous plane and its dielectric spacing. |
| Transition between layers | Document the return connection and any plane change. |
| Adjacent signal layers | Check separation and coupling; orthogonal routing alone is not a guarantee. |
| Manufacturing release | Confirm pressed thickness, copper, laminate grade and agreed tolerance. |
Understand the thickness and line-model limits
Choose the laminate and bonding system from the electrical path, assembly exposure and reliability requirements. FR-4 describes a family rather than a single dielectric constant. Glass style, resin content, frequency and the measurement method can change the value used in a circuit model. A higher Tg does not automatically mean lower insertion loss, better copper adhesion or a higher continuous service temperature.
For a routine rigid construction, identify the manufacturer and complete grade, approved thickness options and copper foil. For longer high-speed channels, compare the loss model, copper roughness and actual channel length before selecting a low-loss material. A short local bus and a long connector-to-connector route may not need the same material expenditure. Hybrid construction requires a separate bonding and compatibility review.
Keep material substitutions under engineering control. A purchasing description that says only 鈥淔R-4, high Tg鈥� cannot preserve an impedance model or a qualification record. Ask for proposed alternatives before release, compare the required properties, and record the accepted construction in the drawing revision. Supplier data supports selection; it does not certify the finished board or establish current stock.
Use the right thickness in each calculation
Before using the planner, check whether each catalogue core dimension includes copper. The following limits describe the worksheet, rather than additional material-selection rules.
The planner counts finished outer copper once and counts each inner copper layer separately. Its candidate search uses symmetric dielectric gaps to expose an initial thickness solution. It does not model resin flow, copper-area fill, glass nesting or pressing shrinkage. After choosing a candidate, replace reference values with the fabricator鈥檚 proposed pressed thicknesses and record the actual laminate and prepreg constructions.
The optional outer-line estimate uses an entered design Dk and a zero-thickness microstrip model. It excludes solder mask, etch shape, roughness and differential coupling. Use it to understand scale, then request the fabricator鈥檚 field-solver table with signal/reference layers, finished copper, line width and pair spacing. An arithmetic thickness match is not an impedance guarantee.
Advanced: material-library candidates, microstrip and budget models
The existing specialist planner retains its reference construction library and model-specific controls. Its inputs are separate from the brief worksheet. Enter your intended construction and read each model鈥檚 limits before using its result.
4 Layer PCB Stackup Planner
Review the interconnect and inspection plan together
Start with a drill map that distinguishes through holes, blind holes, buried connections, microvias and any backdrill operation. Each needs a depth or layer span, diameter basis and acceptance definition. The planner鈥檚 depth-to-drill ratio is a geometric check using pre-plating drill diameter; it is not a universal plating capability limit and must not be confused with finished hole diameter.
For a conventional multilayer, inner circuits are imaged and inspected before lay-up, bonding and outer-layer processing. The required number of press cycles comes from the interconnect architecture. Additional copper layers do not automatically mean sequential lamination, stacked microvias or via-in-pad. If those features are required, include filling, capping and registration requirements in the quote scope.
Match the test to the requirement. Netlist continuity and isolation do not measure insertion loss or validate a return path. Controlled-impedance coupons need an agreed structure and test method; RF measurements need defined ports, fixtures and calibration boundaries. Dimensional inspection and relevant cross-sections should represent the actual construction and hole families. Decide which records accompany the first build and subsequent orders.
Compare complete constructions when reviewing price
Layer count is one cost driver, not a pricing formula. Material consumption, usable panel area, copper, drill families, lamination sequence, surface finish, inspection, electrical test and quantity all contribute. A narrow board can fit a panel efficiently or waste more area after process rails and coupons are included. Small quantities spread setup and fixture costs across fewer boards.
Ask comparable suppliers to quote the same material definition, finished thickness, copper, finish, hole map and acceptance scope. Separate one-time engineering or tooling from repeat fabrication. Also separate bare-board manufacture from component sourcing and assembly. A cheaper quote may simply omit a coupon, a test report or a finish requirement that another quote includes.
The optional budget uses your entered setup, fabrication-per-board and batch test allowances. It has no live factory tariff and makes no claim about current market prices. Its range is an uncalibrated planning scenario, not a statistical confidence interval. Complex and unsupported constructions produce a useful engineering brief instead of a misleading instant price. Contact remains available before any calculation.
Make the first enquiry useful, even with preliminary files
Send the board outline and mechanical requirements, fabrication artwork, drill data, quantity, intended revision and the target thickness. Include the layer order with copper weight or thickness, material grade, core and bonding-layer descriptions. Identify open decisions explicitly. A preliminary design is enough to start a review if it is clearly distinguished from a released manufacturing package.
List controlled-impedance net classes with their signal layer, reference layer, target, tolerance and intended test method. Provide the proposed via spans, finished hole sizes and any backdrill limits. For selective finishes, identify the physical regions and required deposit specification; a broad term such as gold finish does not distinguish wear contacts from solderable pads.
If assembly is included, add the BOM with manufacturer part numbers, placement data, assembly drawing and test expectations. Review connector soldering, thermal exposure and mechanical support where they affect the board. Download the current planner output and attach it with the drawing. The Contact link opens the enquiry page; it does not silently upload files or transfer calculator inputs.
Continue with the decision still open
| Next page | Use it when |
|---|---|
| Compare multilayer PCB routes | You are reconsidering the layer count. |
| 4-layer manufacturing and quote preparation | You need the fabrication scope and quote requirements. |
| Compare a 6-layer alternative | Use the same board outline, material and via constraints. |
| Define controlled-impedance geometry | You need trace, reference, tolerance and coupon requirements. |
| PCB manufacturing services | Review the wider fabrication route. |
| Review thermal material requirements | Assembly exposure or reliability requirements influence the laminate. |
| Check rigid PCB manufacturing conditions | Compare the complete construction against the documented process envelope. |
4 layer PCB questions
What does 4 layer PCB mean?
It counts 4 conductive copper layers. Solder mask and silkscreen do not add copper layers. The count alone does not specify the dielectric schedule, material grade, via structure or how many layers are used for signals.
Is the recommended stackup ready to manufacture?
No. It is a reference construction and thickness check. Ask the fabricator to confirm material availability, pressed dielectric values, finished copper, impedance geometry and the complete fabrication route before release.
Why does the tool show more than one thickness candidate?
Different core and PP combinations can approach the same finished thickness while changing the outer signal-to-reference gap. The best electrical and manufacturing choice is not necessarily the smallest numerical difference.
Does 2116 always have the same thickness?
No. The cloth designation alone is insufficient. Resin content, the supplied construction and the actual pressed condition matter. The reference library distinguishes entries with different resin contents and labels the original table date.
Can I get a quote without finishing the calculator?
Set the outer dielectric gaps and actual material before routing controlled impedance; nominal board thickness alone is insufficient. Send available artwork, quantity and open questions through Contact. A useful first review can start before the final stackup is approved.
Will adding layers automatically improve signal integrity?
Only if the allocation helps the actual circuit. Poor references, split-plane crossings, unsuitable transitions and long detours can remain in a board with many layers. Review placement, routing and the return path together.
Engineering references
The linked original documents support material identification and layout principles. Use the current exact-grade and device guidance for a released project. They do not certify a 吃瓜tv production process.
Download the editable engineering review sheet. Complete the project-specific fields and attach it manually when requesting a review. No project files or values are automatically sent.
Engineering source context
Use the current exact-product documentation for a released design. These sources support the named principles; they do not certify a 吃瓜tv process.