RT/duroid 5870 PCB Manufacturing & Line Design
Check microstrip or symmetric stripline, compare 5880 at fixed geometry and prepare a repeatable 5870 construction specification.
Design & Specify Your RT/duroid 5870 PCB
Check a design decision. Record assumptions. Prepare a useful fabrication enquiry.
Start with a supplier thickness
Choose a catalogue core or keep a custom design dimension. Applying a thickness changes the local microstrip height, not the finished board thickness.
No catalogue construction applied yet.
Compare two thickness choices at the same impedance
This Line design tab uses a preliminary zero-thickness, quasi-static model. For finite copper or GCPW, use the separate advanced calculation below. This reference model excludes solder mask, finite copper, roughness, vias and connectors. Confirm the exact stackup with a field solver and fabricator. Frequency is not a material-dispersion model. Microstrip h / free-space wavelength must be 鈮� 0.05.
Width, dielectric height and model-Dk sensitivity
Reference ground below 鈥� schematic, not an approved stackup
Finite-copper microstrip and grounded CPW
A mask or cover changes the field distribution. This worksheet records it for solver review rather than applying an unsupported universal Dk adjustment.
Build a layer-by-layer discussion stackup
Select a copper-layer count, then name and dimension every core and bond layer. Blank thicknesses are unresolved; they are never silently treated as zero.
Loading an example replaces this worksheet. Copper defaults are illustrative. Bond product, cured thickness and internal support thickness must be supplied; no lamination approval is implied.
View the layer-sequence schematic
Transfer uses only a named material core between L1 RF and L2 ground. No averaged mixed-dielectric Dk is created.
Shares the inputs in Line design. Change the geometry there before calculating this task.
Download the brief and attach it with your design files. Contact opens the enquiry page; parameters and files are not automatically transferred. Email opens a draft for you to review.
No enquiry has been sent. Calculations remain in this browser.
RT/duroid 5870 thickness and copper options
吃瓜tv can procure Rogers-offered materials and thicknesses. Select the exact construction for your request; available stock, copper combination, minimum purchase and delivery date are confirmed for the order.
| Nominal dielectric | Metric conversion | Supplier thickness tolerance | Construction note |
|---|---|---|---|
| 5 mil | 0.1270 mm | 卤 0.5 mil | |
| 10 mil | 0.2540 mm | 卤 0.7 mil | PDF prints 0.252 mm for 0.010 inch; exact conversion 0.254 mm is used by the tool. |
| 20 mil | 0.5080 mm | 卤 1.5 mil | |
| 31 mil | 0.7874 mm | 卤 2 mil | |
| 62 mil | 1.5748 mm | 卤 3 mil |
These are supplier catalogue dielectric dimensions, not finished PCB thickness or inventory. Metric values above are converted from the listed inch dimensions. A catalogue dielectric tolerance is not a guaranteed impedance tolerance.
Specify the cladding separately
- Electrodeposited copper, 0.5 oz (18 碌m nominal) 鈥� Base foil, not finished plated copper. Confirm the thickness/foil combination and roughness for the actual order.
- Electrodeposited copper, 1 oz (35 碌m nominal) 鈥� Base foil, not finished plated copper. Confirm the thickness/foil combination and roughness for the actual order.
- Rolled copper, 0.5 oz (18 碌m nominal) 鈥� Base foil, not finished plated copper. Confirm the thickness/foil combination and roughness for the actual order.
- Rolled copper, 1 oz (35 碌m nominal) 鈥� Base foil, not finished plated copper. Confirm the thickness/foil combination and roughness for the actual order.
Process Dk tolerance is a supplier-test specification, not an automatic Design Dk uncertainty band. Additional thicknesses 3.5鈥�375 mil are described in varying increments; no common tolerance is given. The broad copper-weight sentence on PDF page 1 includes an inconsistent micrometre value. Standard copper selections use the explicit page-2 table.
. Procurement availability confirmed by 吃瓜tv on 17 October 2026; this is not a stock or lead-time promise.
Lock the reference structure before comparing a replacement
A repeat build needs more than the laminate grade from a previous purchase order. Preserve the released stackup revision, finished copper, foil, reference planes, process allowances and acceptance method. A material comparison is useful only when those conditions are visible. The comparison task keeps the original line geometry fixed before showing the alternative equal-impedance width.
Microstrip and stripline use different height definitions
For microstrip, enter the local signal-to-ground dielectric height h. For symmetric stripline, enter the total ground-to-ground spacing b, with the trace centered between the planes. Do not enter half the spacing or reuse the overall board thickness without checking the cross-section.
Use a controlled drawing and material specification to identify the ordered construction. A product photograph cannot verify laminate grade, dielectric properties or inspection results.
Keep the material data and design model connected
| Reference quantity | Value | How to use it |
|---|---|---|
| Process Dk | 2.33 卤 0.02 | Supplier test reference; do not use its tolerance as a guaranteed Design-Dk tolerance. |
| Design Dk | 2.33 | Starting model value, subject to exact construction and appropriate frequency data. |
| Df at 10 GHz | 0.0012 | Dielectric reference only; not total circuit insertion loss. |
| TCDk | -115 ppm/掳C | Typical coefficient; not a life or system-qualification model. |
Process Dk / Df: 10 GHz, 23 掳C, IPC TM-650 2.5.5.5; Design Dk: 8鈥�40 GHz differential phase length; TCDk: 鈭�50 to 150 掳C. Typical source values, not finished-board acceptance limits. In this workbench, Dk and frequency are explicit inputs; no dispersion curve is inferred. Catalogue constructions must be checked for the actual order.
Data checked 17 October 2026 against the . Use the current supplier document when releasing a design.
Choose a layer structure for the RF task
Start with the signal and its reference plane, then add routing, power and mechanical requirements. The workbench records each conductor and dielectric separately. Example layer allocations are discussion starting points, not released manufacturing constructions.
| Architecture | Decision to resolve | Useful next step |
|---|---|---|
| Two copper layers | RF signal on one face, continuous ground on the other. The core is the local dielectric; finish, mask and launches remain separate inputs. | Use the line and thickness comparison tools above. |
| Four copper layers | Define the outer RF cores and central bonding construction; decide whether both faces carry RF. | Review four-layer PCB fabrication and four-layer stackup choices. |
| Six copper layers | Keep RF paths beside continuous grounds while allocating internal power and routing. Specify the FR-4 or RF support core and both bond layers. | Define a six-layer PCB build; use the six-layer stackup guide for layer allocation. |
| Eight or more layers | Resolve additional routing, via transitions, lamination sequence and mechanical balance before freezing dimensions. | Review eight-layer fabrication requirements or discuss a specific construction. |
| RF / FR-4 hybrid or metal-backed build | Specify every bond product, cured thickness, interface and thermal requirement. The online tool does not approve a press cycle or adhesive system. | Use the Rogers multilayer construction guide. |
For other layer counts, follow the multilayer PCB manufacturing route. Material-specific construction and RF acceptance remain part of the RT/duroid 5870 enquiry.
Changing from 5870 to 5880
Compare both impedance shift at unchanged artwork and the width needed to recover the nominal impedance. The result is an electrical planning comparison, not an approval to change laminate, bonding, cladding or the product qualification record.
Repeat-build evidence
Keep the material designation, released artwork and stackup, inspection records, coupon results and any agreed deviations connected by revision. If the original construction is not known, investigate it before describing a new order as identical.
A starting geometry you can reproduce
For a 50 惟 exposed microstrip using model Dk 2.33, local dielectric height 0.2540 mm and a 10 GHz calculation frequency, this model gives a starting width of 0.7556 mm and effective permittivity 1.9714. A uniform 50 mm path has an unwrapped phase of 843.03掳. These are calculated examples, not measured board results.
Reproduce the values in Line design, then change one input. Before release, replace the example with the agreed construction, include finite copper and mask in an appropriate solver, and confirm how the finished board will be inspected.
Turn design choices into acceptance requirements
| Decision | Include in the RFQ | Resolve before release |
|---|---|---|
| Reference planes | Microstrip h or symmetric-stripline b | Does the drawing use the same dimension as the model? |
| Repeat construction | Exact grade, thickness, foil and stackup revision | Which items are fixed and which require approval to change? |
| Material alternative | 5870 baseline and 5880 candidate | Is the comparison at fixed geometry or fixed impedance? |
| Order release | Artwork, coupon and inspection revision | Can requirements and received records be traced to the same release? |
Ask for confirmation against the released construction and files. The planning result is a discussion aid; the accepted drawing, quotation and inspection scope define the order.
Connect the drawing, the board and its test record
For your RT/duroid 5870 build, identify the evidence needed before ordering. A useful review connects the same material designation and drawing revision across the stackup, physical inspection and electrical test. The catalogue photograph on this page gives construction context; it does not establish order-specific material identity or RF performance.
Illustrative evidence workflow, not a sample inspection report. Request applicable records and agree availability before purchase. RF measurement scope, calibration, fixture correction and environmental testing must be specified; they are not automatically included in a continuity test.
Start the enquiry at your current design stage
| Your stage | Useful starting information | Request |
|---|---|---|
| Selecting a material | Frequency band, mechanical envelope, environment and material candidates. Final artwork is not needed to describe the question. | Check material availability |
| Designing the PCB | Proposed layer sequence, RF reference planes, dielectric / copper dimensions and unresolved requirements. | Request a stackup review |
| Ready for fabrication | Released artwork and drill files, drawing revision, quantity, material specification and acceptance requirements. | Get a quote for this build |
Use the workbench to download a brief if it helps explain the project, or contact the team directly. These links open Contact; they do not upload files or automatically submit tool inputs. Ask the team to confirm the available review scope and quotation requirements.
RT/duroid 5870 design & procurement questions
Can I use this stripline model for an off-center trace?
No. It assumes a centered zero-thickness conductor between two ground planes. Asymmetric, broadside-coupled or mixed-dielectric structures need a suitable field solver.
Why does the 5880 comparison give two answers?
One answer preserves the original width and shows the impedance change. The other changes width to recover the original impedance. They represent different design decisions.
Are listed thicknesses proof of stock?
No. Supplier catalogue constructions are not a stock or delivery promise. Confirm the actual purchasable construction for the order.
Continue with the decision you need to make
For a different material route, compare the Rogers material families. Use the relevant construction or acceptance guide when the requirement goes beyond this material-specific model.
Model references & limits
The reference line tool uses a zero-thickness approximation; the advanced tool separately identifies finite-copper and grounded-CPW models. Corner results are deterministic bounds from your entered scenarios; no statistical capability is inferred. Measurements and a construction-specific field solver remain the appropriate next steps for release.
- : material values and test conditions.
- : Hammerstad鈥揓ensen geometry formulation.
- : zero-thickness characteristic impedance and effective-width correction.
- : quasi-static mapping and limited finite-copper correction.
- : implementation convention cross-check; not a measured accuracy claim.