Via-in-pad means that a via is located within a component’s solder land. It describes placement, not a single filling process. VIPPO, or via-in-pad plated over, is a particular implementation that presents a plated surface over a filled via. Selecting it requires agreement on the package footprint, via structure, filling and capping process, and assembly requirements.
The right choice is not a universal ranking of 鈥渢raditional鈥� and 鈥渁dvanced鈥� vias. Compare the routing problem, solder-joint needs, thermal function, process complexity and verification plan. A short escape route may be useful, but it does not automatically establish signal integrity or long-term reliability. This guide separates the choices that are often combined under the term via-in-pad.
Separate via location from the layer connection
A through via passes through the board. A blind via connects an outer layer to an inner layer; a buried via connects inner layers without opening at an external surface. Microvia structures must be defined by their geometry, layer connection and applicable specification, rather than by diameter alone. Any proposed structure must suit the selected stackup and fabrication route.
Via-in-pad is another design attribute: where the opening lies relative to the solder land. It does not tell the fabricator whether the interconnect is a through via, a laser microvia or part of a more complex HDI structure. State both the layer connections and the treatment required at the component land.
Keep nearby but distinct design decisions separate. An annular-ring requirement concerns the relationship between a drilled feature and its copper land. A solder-mask opening describes the surface exposure. Filling and capping describe processing of the via. None can be inferred reliably from the phrase 鈥渦se VIP鈥� alone.
Choose the pad treatment for the assembly task
An open via in a solder land can provide a path for solder to leave the intended joint during reflow. Whether an open thermal-via arrangement is acceptable depends on the component guidance and assembly design. Do not apply a BGA escape recommendation indiscriminately to a large exposed thermal pad, or assume that every thermal via must use the same fill process.
distinguishes tented, plugged, filled, and filled-and-capped vias for its fine-pitch package context. It describes filled-and-capped vias as planarized and plated after filling. Use that distinction, but obtain the current application guidance for your actual package; the report’s package-specific dimensions are not universal design rules.
| Term in the drawing | What still needs agreement |
|---|---|
| Tented or masked via | Which side is covered and whether the treatment suits the soldering and inspection task. |
| Filled via | Fill material/process, affected vias and acceptance requirements; filling alone does not specify a solderable cap. |
| Filled and copper-capped via | Filling, planarization, cap and final finish requirements for the component land. |
| Copper-filled microvia | Microvia geometry, plating route, layer sequence and any stacked interface requirements. |
A nonconductive resin fill is compatible with a conductive plated barrel and copper cap; 鈥渘onconductive fill鈥� does not mean the via has no electrical path. Conversely, resin filling a plated through via and copper filling a microvia are not interchangeable descriptions. Review via filling options with the proposed structure rather than selecting a process by name alone.
Compare routing options before choosing VIPPO
A dog-bone escape moves the via outside the component land and connects it with a short trace. It can be a practical route when pitch and spacing allow. Via-in-pad may free routing area or reach an inner layer directly, but it adds requirements at the solder land. Compare both against the actual component footprint and layer plan.
For a BGA, check pad pitch, escape channels, mask geometry, via lands and return paths together. The BGA via-in-pad guide addresses that package context. A layout should not acquire finer vias, additional sequential laminations or stacked structures merely because they are available; each should solve an identified routing or interconnect problem.
Through, blind and buried routes have different manufacturing implications. Review the blind-versus-buried via distinction when selecting layer access. A blind structure can shorten a connection, but the complete signal and return geometry determines electrical behavior. Claims of lower noise or improved signal integrity require analysis of the design, not just a via label.
For a thermal pad, consider the heat-flow path through the whole assembly and follow the component’s recommended land and paste strategy. A change in via count, fill or copper distribution can also change soldering behavior. Confirm the footprint and stencil approach with the assembler instead of using via technology as a substitute for a thermal or assembly review.
Put the required structure in the release documents
Identify the via groups that require special treatment, their layer connections, nominal drilled geometry and applicable tolerances. Distinguish the drilled feature from a finished open hole; a filled structure should not be described solely by a finished-hole callout intended for an unfilled through hole. Let the fabricator confirm the required production dimensions against the intended final structure.
Specify which pads must be filled, planarized and capped, and identify any relevant flatness, surface or acceptance requirements. Avoid inventing a cap thickness or allowable void limit from a generic article. Use the applicable specification, device needs and supplier agreement. A finish name alone does not define all the underlying via treatment.
Provide the stackup, drill information, copper and mask data, fabrication notes and assembly footprint from the same released revision. If the CAD system represents a filled via using a standard drill symbol, make the special treatment unambiguous in the drawing and via schedule. Review how the requirement survives any file conversion.
Before order release, use the PCB fabrication review to confirm that the proposed structure, filling and capping instructions can be built and inspected as specified. Keep the closest via and BGA topic guidance with the design package; the commercial review does not replace package-specific design rules or product validation.
Agree verification instead of assuming reliability
Review verification with reference to the actual stackup and failure risks. Bare-board connectivity, surface inspection, cross-sections and thermal-stress testing answer different questions. Passing one check does not imply that every latent interface weakness has been excluded.
describes latent failures that may escape traditional acceptance inspection and appear after subsequent thermal exposure. This supports discussing a structure-appropriate verification plan; it is not evidence that all stacked microvias fail or that all alternative structures are safe.
Ask which coupons or product features represent the proposed construction, what stresses and electrical monitoring will be applied where required, and which records accompany the lot. Agree how a change in materials, microvia arrangement or process sequence will be reviewed before it is introduced into a repeat build. Avoid treating a photograph of a cross-section as a complete qualification report.
Include the assembler in the review of pad condition, solder behavior and relevant reflow exposure. Where a change affects joint formation, use appropriate assembly trials and inspection for the package. The scope should follow the product risk and acceptance requirements, not an unqualified promise that via-in-pad is always more reliable.
For an enquiry, send the stackup, via schedule and component footprint, along with quantity and required verification records. Identify unresolved choices rather than approving an ambiguous 鈥淰IPPO鈥� note. The useful outcome is an agreed interconnect construction and acceptance plan, not simply the most complicated via option.