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Choose a thickness without hiding the dielectric schedule

The 10-layer selector holds the copper count fixed. Start with the mechanical target and finished copper, then compare candidate core and prepreg schedules. The displayed difference is an arithmetic nominal difference, not a manufacturing pass or fail. There is no universal acceptable thickness tolerance; the drawing and supplier proposal define it.

A thinner outer bonding gap often allows a narrower impedance trace, but that does not make the thinnest construction the best choice. Copper pattern fill, voltage spacing, material availability and pressing control also matter. Compare the outer signal-to-plane distance separately from a thicker central region that provides mechanical thickness.

The reference table identifies glass style and resin content for Isola FR406. It is not a statement that the fabricator stocks each combination. Cores above the listed reference-table range are explicitly nominal engineering targets. Keep the selected proposal with its actual supplier construction rather than copying only the nearest total thickness.

10 layer PCB stackup design tool

Select a target thickness, compare construction candidates where available, and inspect the numbered copper layers. You can change every dielectric thickness in the row editor. The finished total includes entered copper and coating allowances. The optional width estimate uses your own approved design Dk; it is an initial single-ended microstrip comparison, not a field-solver or differential-pair result.

10-layer thickness, core and prepreg examples

Start with the mechanical constraint, then check whether the electrical allocation can fit within it. A connector stack height or enclosure is a target; it does not establish the availability of a particular prepreg construction. In a conventional even-layer foil build, cores and bonding gaps can be counted before the exact materials are chosen. Odd-count examples below are geometry allocations only.

Planning examples: 35 ?m finished surface copper, 18 ?m inner copper, zero separate coating allowance. These are reference candidates, not stocked or released constructions. A difference is not an approved tolerance. The tool can change the target and edit every dielectric row. Values above the FR406 reference core range are nominal design targets.

More interface routing without losing reference quality

A ten-layer layout often starts when an eight-layer plan is congested or needs another reference allocation. Compare the same connector map on both counts. If two more layers shorten difficult channels and preserve plane continuity, the electrical benefit may justify the build; if dense vias consume those routes, the improvement may be small.

Control the five bonding regions in a ten-layer plan

A ten-layer foil-build concept contains four cores and five PP bonding gaps. The central PP region sits between L5 and L6. An example that repeats one PP at every position is useful for thickness accounting, but the final build can require different mirrored outer and inner schedules to satisfy the actual electrical design.

Assign the purpose of the central layer pair explicitly. It may contain routing, planes or a deliberately coupled power/ground structure depending on the circuit. Do not call it a stripline merely because it is internal; the surrounding reference layers and their separation determine the transmission-line structure.

Check every signal layer change against the reference transition. A ten-layer board offers more destination layers, which can create more unused barrel below or above an active connection. Whether that matters depends on the channel and structure. Request a via model or appropriate review before choosing backdrill, blind or buried processing purely from the number ten.

Send a layer-pair impedance list with the ten-layer table. Include outer and inner copper definitions, dielectric material identities and any permitted fabrication compensation. If a supplier changes the bonding schedule, review both the new thickness sum and the nets affected by the moved planes. A construction approval and an electrical approval should describe the same revision.

Select the resin system, not just a Tg label

Choose the laminate and bonding system from the electrical path, assembly exposure and reliability requirements. FR-4 describes a family rather than a single dielectric constant. Glass style, resin content, frequency and the measurement method can change the value used in a circuit model. A higher Tg does not automatically mean lower insertion loss, better copper adhesion or a higher continuous service temperature.

For a routine rigid construction, identify the manufacturer and complete grade, approved thickness options and copper foil. For longer high-speed channels, compare the loss model, copper roughness and actual channel length before selecting a low-loss material. A short local bus and a long connector-to-connector route may not need the same material expenditure. Hybrid construction requires a separate bonding and compatibility review.

Keep material substitutions under engineering control. A purchasing description that says only “FR-4, high Tg” cannot preserve an impedance model or a qualification record. Ask for proposed alternatives before release, compare the required properties, and record the accepted construction in the drawing revision. Supplier data supports selection; it does not certify the finished board or establish current stock.

Use the right thickness in each calculation

Finished board thickness is the sum of the copper, dielectric and any coating allowance defined in the drawing. The dielectric thickness in a microstrip calculation is only the gap between the signal and its reference plane. Entering total board thickness in that calculation can produce an unusable trace width. State whether a supplied core thickness includes copper before adding the copper rows.

The planner counts finished outer copper once and counts each inner copper layer separately. Its candidate search uses symmetric dielectric gaps to expose an initial thickness solution. It does not model resin flow, copper-area fill, glass nesting or pressing shrinkage. After choosing a candidate, replace reference values with the fabricator’s proposed pressed thicknesses and record the actual laminate and prepreg constructions.

The optional outer-line estimate uses an entered design Dk and a zero-thickness microstrip model. It excludes solder mask, etch shape, roughness and differential coupling. Use it to understand scale, then request the fabricator’s field-solver table with signal/reference layers, finished copper, line width and pair spacing. An arithmetic thickness match is not an impedance guarantee.

Review the interconnect and inspection plan together

Start with a drill map that distinguishes through holes, blind holes, buried connections, microvias and any backdrill operation. Each needs a depth or layer span, diameter basis and acceptance definition. The planner’s depth-to-drill ratio is a geometric check using pre-plating drill diameter; it is not a universal plating capability limit and must not be confused with finished hole diameter.

For a conventional multilayer, inner circuits are imaged and inspected before lay-up, bonding and outer-layer processing. The required number of press cycles comes from the interconnect architecture. Additional copper layers do not automatically mean sequential lamination, stacked microvias or via-in-pad. If those features are required, include filling, capping and registration requirements in the quote scope.

Match the test to the requirement. Netlist continuity and isolation do not measure insertion loss or validate a return path. Controlled-impedance coupons need an agreed structure and test method; RF measurements need defined ports, fixtures and calibration boundaries. Dimensional inspection and relevant cross-sections should represent the actual construction and hole families. Decide which records accompany the first build and subsequent orders.

Compare complete constructions when reviewing price

Layer count is one cost driver, not a pricing formula. Material consumption, usable panel area, copper, drill families, lamination sequence, surface finish, inspection, electrical test and quantity all contribute. A narrow board can fit a panel efficiently or waste more area after process rails and coupons are included. Small quantities spread setup and fixture costs across fewer boards.

Ask comparable suppliers to quote the same material definition, finished thickness, copper, finish, hole map and acceptance scope. Separate one-time engineering or tooling from repeat fabrication. Also separate bare-board manufacture from component sourcing and assembly. A cheaper quote may simply omit a coupon, a test report or a finish requirement that another quote includes.

The optional budget uses your entered setup, fabrication-per-board and batch test allowances. It has no live factory tariff and makes no claim about current market prices. Its range is an uncalibrated planning scenario, not a statistical confidence interval. Complex and unsupported constructions produce a useful engineering brief instead of a misleading instant price. Contact remains available before any calculation.

Make the first enquiry useful, even with preliminary files

Send the board outline and mechanical requirements, fabrication artwork, drill data, quantity, intended revision and the target thickness. Include the layer order with copper weight or thickness, material grade, core and bonding-layer descriptions. Identify open decisions explicitly. A preliminary design is enough to start a review if it is clearly distinguished from a released manufacturing package.

List controlled-impedance net classes with their signal layer, reference layer, target, tolerance and intended test method. Provide the proposed via spans, finished hole sizes and any backdrill limits. For selective finishes, identify the physical regions and required deposit specification; a broad term such as gold finish does not distinguish wear contacts from solderable pads.

If assembly is included, add the BOM with manufacturer part numbers, placement data, assembly drawing and test expectations. Review connector soldering, thermal exposure and mechanical support where they affect the board. Download the current planner output and attach it with the drawing. The Contact link opens the enquiry page; it does not silently upload files or transfer calculator inputs.

Continue with the decision that remains open

10 layer PCB questions

Engineering references

The linked original documents support material identification and layout principles. Use the current exact-grade and device guidance for a released project. They do not certify a 吃瓜tv production process.