The general circuit impedance formula is Z(f) = V(f)/I(f), using complex voltage and current phasors at the same frequency. Write the result as R + jX or as magnitude and phase. The familiar square-root expression for a series RLC network gives its magnitude; it is not a universal formula for every circuit or PCB transmission line.
This guide connects calculation with measurement. It shows how to choose a network model, check a numerical answer, select an instrument method and distinguish lumped-circuit impedance from controlled trace impedance. The numerical examples are hypothetical, independently calculated reference cases. They are not measurements of a customer board, component qualification or proof of a particular manufacturing capability.
Choose the formula that matches the circuit
Keep resistance, reactance, magnitude and phase separate
In sinusoidal steady state, impedance describes both amplitude ratio and phase relationship. With the usual 别镑(箩蝇迟) convention, an ideal resistor has ZR = R, an inductor has ZL = j蠅L, and a capacitor has ZC = 1/(j蠅C) = 鈭抝/(蠅C). Here 蠅 = 2蟺f, frequency is in hertz, inductance in henries and capacitance in farads.
For Z = R + jX, the magnitude is |Z| = 鈭�(R虏 + X虏) and phase is 胃 = atan2(X,R). A positive imaginary part is inductive under this convention; a negative one is capacitive. Use a quadrant-aware phase function. An amplitude-only voltage-to-current ratio gives the magnitude when the signals are measured consistently, but it cannot recover phase by itself.
Use either RMS or peak amplitudes consistently in the ratio. Dividing peak voltage by RMS current introduces a scaling error even if the instrument readings are individually correct. For nonsinusoidal waveforms, a single ratio of total RMS values generally does not describe the complete frequency-dependent impedance. Analyze the relevant frequency components or use an appropriate small-signal measurement.
Add impedances in series and admittances in parallel
Series elements carry the same current, so their complex impedances add. For an ideal series RLC circuit, Z = R + j(蠅L 鈭� 1/(蠅C)). Its magnitude is therefore 鈭歔R虏 + (蠅L 鈭� 1/(蠅C))虏]. This is the expression often presented as 鈥渢he circuit impedance formula,鈥� but the series connection and ideal-component assumptions are essential.
For parallel branches, add admittances: Y = 1/Z and Ytotal = 危(1/Zk). Then invert the complex sum. An ideal resistor, inductor and capacitor all connected in parallel give Y = 1/R + j(蠅C 鈭� 1/(蠅L)). The impedance magnitude is 1/鈭歔(1/R)虏 + (蠅C 鈭� 1/(蠅L))虏]. Do not replace the conductance term with a squared reciprocal resistance before squaring it again.
A mixed network must be reduced according to its actual nodes. Two components drawn side by side are not necessarily parallel; they must share both terminals. When the network contains coupling, dependent sources or active devices, simple series-parallel reduction may be insufficient. Use nodal analysis or a suitable circuit model instead of forcing the drawing into an inappropriate shortcut.
Work through two examples and a frequency check
Series RLC: calculate the complex answer first
Assume R = 100 惟, L = 10 mH, C = 1 碌F and f = 1 kHz. Convert the component values before calculating: 10 mH is 0.010 H and 1 碌F is 0.000001 F. The inductive reactance is about 62.832 惟, and the magnitude of capacitive reactance is about 159.155 惟.
The net reactance is 62.832 鈭� 159.155 = 鈭�96.323 惟. Thus Z = 100 鈭� j96.323 惟, |Z| 鈮� 138.846 惟 and 胃 鈮� 鈭�43.927掳. For a 1 V RMS sinusoidal voltage across this network, current magnitude is approximately 7.202 mA RMS. The negative impedance phase means current leads voltage in this example.
At the ideal series resonance, f0 = 1/(2蟺鈭歀C) 鈮� 1591.55 Hz, the inductive and capacitive reactances cancel. The ideal impedance becomes the 100 惟 resistance. This does not make the inductor and capacitor disappear physically: they still exchange energy, carry current and may develop significant individual voltages. Component loss, parasitics and tolerances change the practical response.
Parallel RC: invert the sum, not the individual magnitudes
For a separate example, place a 1 k惟 resistor in parallel with a 100 nF capacitor at 1 kHz. The admittance is 0.001 + j0.000628319 S. Inverting that number gives approximately 716.957 鈭� j450.477 惟. Its magnitude is about 846.733 惟, with a phase of 鈭�32.142掳. Adding 1000 惟 to the capacitor鈥檚 reactance magnitude would describe neither this parallel network nor its current.
A useful self-check is to inspect limiting behavior. At sufficiently low frequency, an ideal capacitor in this parallel RC network draws little AC current, so the impedance approaches the resistor value. As frequency increases, the capacitive branch admits more current and the magnitude decreases. If a calculation predicts the opposite trend for this ideal network, recheck units, topology and the reciprocal operation.
provides a reference for the series phasor model. For a practical design record, keep the complex result as well as its magnitude, frequency and assumed component values. Reporting only 鈥�139 ohms鈥� discards the information needed to distinguish the example from a nearly pure resistor.
Use simulation as a model check
For a linear network, a small-signal AC simulation can sweep frequency and compute port voltage divided by port current. Check the simulator鈥檚 current-direction convention; a reversed reference can change the apparent sign. Around an active circuit, the DC operating point determines the linearized small-signal model. That result is not automatically the circuit鈥檚 response to a large startup transient or saturation event.
Start with ideal values to verify the hand calculation, then introduce documented parasitics and realistic models. Compare the resulting changes against a specific question: resonance movement, loss, input loading or a suspected fixture contribution. A simulation that matches one measured point does not establish that its model remains valid across the entire frequency and operating range.
Measure at a defined frequency and reference plane
Select a method for the impedance range and bandwidth
An LCR meter, impedance analyzer, vector network analyzer and oscilloscope-based voltage/current method do not have identical useful ranges or error sources. Choose a method compatible with the expected impedance, frequency, signal level and fixture. The describes measurement methods, equivalent circuits and compensation. Follow the actual instrument and fixture instructions rather than treating one setup as universal.
Record the measurement plane: component terminals, a connector, test pads or the end of a cable. Leads, connectors and fixtures between that plane and the instrument can add resistance, inductance and capacitance. Compensation or calibration must correspond to the selected setup and plane. Changing a fixture after calibration can invalidate the basis of the comparison.
Understand the voltage/current method before wiring it
One low-frequency laboratory approach places a characterized sense impedance in series with a passive device under test and determines current from the voltage across that sense element. If its behavior is adequately resistive, I = Vsense/Rsense; otherwise use its complex impedance. Measure the DUT voltage and the sense voltage with the phase relationship preserved, then calculate the complex ratio.
The wiring is part of the measurement. Common-ground oscilloscope channels cannot be connected as independent floating voltmeters. An inappropriate ground clip can short a node or alter the circuit. Use a suitable differential arrangement or an instrument method designed for the measurement, and respect its voltage and common-mode limits. This discussion is not a procedure for connecting ordinary probes directly to mains circuitry.
Choose the sense element so that its signal can be resolved without excessively disturbing the DUT鈥檚 operating condition. Account for source impedance, probe loading and channel mismatch. Measure a known reference component over the same frequency range to expose gross setup errors before attributing every discrepancy to the board being investigated.
Separate changing conditions from measurement instability
Temperature, DC bias and AC test level can change the component itself. Poor contact, an unsuitable equivalent-circuit mode or a moving cable can change the measurement. Record these separately. A capacitor measured with a small AC stimulus at zero bias may not represent its effective capacitance on a biased power rail; a warm inductor may differ from its initial bench reading.
Repeat the measurement with the same setup, then deliberately change one relevant condition. Preserve raw magnitude and phase data rather than only a derived capacitance or inductance display. The illustrates how calibration and fixture compensation depend on the selected method; its specific ranges should not be generalized to other instruments.
Apply the result to a PCB without confusing it with trace impedance
Lumped impedance and characteristic impedance answer different questions
A lumped network model assigns a voltage and current to a defined port. A transmission line distributes inductance, capacitance and loss along its length. Its characteristic impedance is commonly written Z0 = 鈭歔(R鈥� + j蠅L鈥�)/(G鈥� + j蠅C鈥�)], using per-unit-length parameters. For a low-loss approximation it approaches 鈭�(尝鈥�/颁鈥�). It is not the DC resistance measured end to end along a copper trace.
Whether a route needs transmission-line treatment depends on signal transition time and propagation behavior, not simply a low clock-frequency label. Trace geometry, dielectric spacing, material properties, reference continuity and the coupled partner affect the model. The PCB impedance-control page owns the fabrication and geometry task; this article owns circuit calculation and measurement.
For a symmetric coupled pair under the usual modal definition, differential impedance is twice the odd-mode impedance. That relationship requires the relevant coupled-line model; it is not permission to double any isolated trace calculator result. Vias and connector launches introduce three-dimensional discontinuities whose behavior depends on the surrounding geometry and return path. There is no universal via impedance range that validates every board.
Make the next review specific
For a component or network investigation, provide the circuit diagram, port definition, operating point, frequency sweep, calibration method and measured magnitude/phase data. For a controlled-impedance PCB, provide net classes, target values and tolerances, proposed layer references, material and copper construction, and the agreed coupon or measurement requirements. These are different evidence packages even when both use the word 鈥渋mpedance.鈥�
The multilayer construction guide helps organize layer roles and dielectric schedules. Bring the resulting requirements to PCB manufacturing review before release. Manufacturing acceptance of the agreed board construction does not validate every circuit model or guarantee system-level signal integrity.
Discuss Your Impedance Requirements
State whether you need help with a trace construction, an assembled-board measurement or an unresolved model discrepancy. Include the original URL or document revision for the requirement and label any assumed values. That makes the enquiry actionable without requiring a completed calculation or an unsupported claim that a design has already passed.