勛圖tv 繚 ENGINEERING GUIDE
Boundary Scan Testing: Plan JTAG Coverage and Its Limits
Boundary scan testing uses supported device test logic to control or observe selected pins without placing a physical probe on every connection. It is particularly useful when dense packages limit access. The presence of a JTAG header, however, does not mean that every pin, component or product function is covered.
Plan boundary scan at schematic and layout stages. This guide connects chain architecture, device models and realistic coverage reporting. The worksheet records evidence readiness; it does not generate vectors or inspect BSDL files.
Understand what the chain can observe
IEEE 1149.1 defines a test-access architecture used by compliant devices. Practical board tests depend on the cells and instructions implemented by each exact device. Nets between controllable and observable pins may support structural tests; analog nodes, unsupported pins and devices outside the chain require separate analysis.
Programming a device through JTAG is a different task from verifying interconnections. A successful programming operation confirms neither every solder joint nor full product function. Keep programming, structural coverage and functional verification as separate report entries.
Match device models to the released design
Obtain the correct boundary-scan description for the exact device and package. Check configuration-dependent pins, compliance conditions and model revisions. A similar family name is not enough when pin behavior or instructions differ.
Maintain a chain drawing and list device order, supported voltages, reset behavior and any chain segmentation. Ensure the test-access port can be reached in the actual assembled state. The test-point layout guide covers the physical access that remains necessary.
| Review item | What to establish |
|---|---|
| Models | Exact device, package and model revision are required. |
| Chain | Record access, order, power domains and reset conditions. |
| Coverage | State fault model and exclusions, not only a percentage. |
| Correlation | Validate vectors on the supported product configuration. |
Boundary-scan evidence brief
Boundary-scan evidence brief
Use the current inputs and keep the assumptions
Choose the engineering question before entering numbers. Fields begin blank. Load example fills teaching values so you can understand the model; those values are not recommended dimensions, process settings or market prices. The example label remains visible after edits. Reset before preparing a record based entirely on your own project data.
Use the displayed units and keep a reference for each input. Counts must describe the same scope, and measurements must share the declared conditions. A threshold entered by you remains your supplied review condition. The website does not turn it into an IPC limit or an approved product requirement. If the necessary value is unknown, obtain the evidence rather than replacing it with an attractive assumption.
Read the result and its limitations together. An access fraction is not fault coverage, a cost allowance is not a quotation, and a completed evidence checklist is not a safety or quality approval. Negative margins remain visible where the model permits them. They identify a conflict in the entered scenario rather than silently adjusting the result.
Changing an input invalidates the result and disables its download until you run the tool again. The text record contains the inputs, result and limitations. Processing stays in your browser; no CAD files, instruments or certificates are read. No data is automatically transferred to the enquiry form. Download and attach the record manually if useful, or contact 勛圖tv directly without completing the tool.
| Input | What to establish before using it |
|---|---|
| Review reference | Use a nonconfidential revision or scope reference. |
| Exact BSDL / device models | Self-reported status; retain the actual evidence or N/A rationale. |
| Chain and voltage-domain drawing | Self-reported status; retain the actual evidence or N/A rationale. |
| Safe control and device states | Self-reported status; retain the actual evidence or N/A rationale. |
| Fault-model coverage analysis | Self-reported status; retain the actual evidence or N/A rationale. |
| Representative hardware correlation | Self-reported status; retain the actual evidence or N/A rationale. |
| Next action / record reference | Use a nonconfidential reference; this tool does not verify the record. |
Control the board while running structural tests
Other circuit elements can drive a net while the test logic attempts to control it. Establish safe states for resets, clocks, enables and power domains. Isolate or manage conflicting drivers through a reviewed design and test program.
Boundary-scan vectors can affect real outputs. Account for connected loads and external interfaces in the fixture specification. Do not run an unreviewed pattern against an operating system merely because the chain enumerates correctly.
Report coverage by fault model
Name the objects and fault classes in the denominator. A percentage of nets analyzed, pins reachable or interconnect faults detected describes different things. List exclusions and the reason each remains uncovered. Avoid combining these counts with optical inspection into a single unexplained quality percentage.
Pair the analysis with other methods where required. BGA inspection can examine hidden-joint features that electrical structural testing does not describe; functional tests verify selected behavior under the conditions in their program.
Example: chain continuity is only the beginning
An illustrative board contains two compliant devices and one analog sensor. A chain check identifies the two devices correctly. That result establishes a useful access condition, but it does not show that the sensor output path, analog accuracy or high-speed link performance meets the product requirement.
The next step is a reviewed coverage analysis using the netlist and correct models, followed by correlation on real hardware. Keep the uncovered sensor measurements in the functional specification instead of marking the board fully tested.
Maintain the program as the product changes
A replacement component, package change or revised pin configuration can invalidate assumptions without moving the JTAG connector. Version the models, netlist, vectors and fixture mapping together. Record which combinations are released.
When diagnosing a failure, preserve the exact chain response and test log. A broken chain can arise from access, power or device-state problems as well as an interconnection defect. Resolve the evidence before assigning a manufacturing root cause.
Prepare a useful boundary-scan enquiry
Supply the schematic, netlist, BOM with exact device identities, relevant BSDL files, chain drawing, access details and the faults or functions that matter. State whether programming, structural test development or ongoing production execution is requested.
Use the circuit-card test plan to coordinate boundary scan with other stations. A supplier proposal should identify covered objects, exclusions, development responsibilities and how the result is associated with each assembly.
Questions to resolve before the next build
Does a successful JTAG connection prove the board is good? It establishes only the communication or access demonstrated by that operation. It does not automatically prove structural coverage, analog accuracy, every solder interface or product function. Identify the exact test that ran and the objects it observed. This keeps a useful chain check from being overstated when the result is passed from development to purchasing or production.
Can boundary scan replace all test points? That requires a product-specific analysis and is rarely a safe assumption from the device list alone. Power, analog, unsupported pins and high-speed performance may still need other access. Review the chain models and controllability before removing pads, and keep the uncovered functions in the test specification. The result should be an intentional combination of methods with stated limits, not an unexplained reduction in physical access.
Connect structural coverage to the physical test interface
Build the review around a marked assembly rather than an isolated list of pad coordinates. Show the contact side, fitted component envelopes, locating features and places where the fixture can safely support the board. The reviewer needs to see the physical object that will arrive at the station, including connectors, shields and hardware installed before testing.
Next, attach a measurement list. Identify which node or interface supports each required observation and which cannot be reached through the proposed route. Keep the reason for each exclusion: a deliberately unobserved signal, a hidden pad and an unfinished access review are different situations. This distinction prevents a tidy spreadsheet from disguising unresolved testability.
Review tolerance and repeatability with the fixture designer. Board fabrication variation, assembly variation, locating error, probe travel and contact wear interact. A nominally aligned drawing may still produce intermittent contact at the extremes. Ask which representative parts and repeated operations will be used to establish that the interface works consistently.
Keep measurement disturbance visible. A fixture can change loading, grounding, temperature or mechanical strain. A contact arrangement that works for a low-frequency check may not preserve a fast edge or a small analog signal. Identify the measurement path and compare it with an appropriate reference method when the interface can influence the decision.
Define what happens when contact is uncertain. An operator should not have to guess whether a failed result belongs to the board or the fixture. The station needs a controlled way to identify invalid runs, inspect contact conditions and escalate recurring problems. Retrying until a pass appears can hide either a contact issue or a real intermittent failure.
For purchasing, separate the reusable platform from product-specific plates, probes, wiring and programs. Record ownership, storage, spares, revision changes and support. A fixture that is economical for a stable repeated build may require a different commercial arrangement for prototypes that change frequently. Request a scope that makes those future responsibilities explicit.
Before release, reconcile the final board files with the fixture and test program. Retain the supported configuration, validation evidence and open exceptions. When an engineering change arrives, review its effect on access and measurement even if the board outline and commercial part number remain unchanged. The purpose is repeatable evidence from the intended product, not simply a fixture that closes around it.
Standards, source context and limits
Use each reference for its stated scope. Equipment and material documentation applies to the identified product and conditions. A published study describes its own specimens and methods; its settings are not universal production limits. Public standard summaries and revision tables do not replace the controlled normative document.
Agree the applicable standards, revisions, product class where relevant, measurement methods and exceptions before production. Distinguish printed-board requirements, assembly workmanship, laboratory competence and finished-product certification. A method name or photograph does not establish that a supplier holds an accreditation or that a particular test is included in an order.
Archive photographs illustrate relevant boards, equipment or operations from the existing 勛圖tv website. They are not evidence of current equipment ownership or results from your project. Original diagrams explain concepts and measurement boundaries; they are not inspection records or released manufacturing drawings. Confirm the actual service and reporting scope in the project review.
