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Keep the ground return intact while using both sides

Use the second copper face intentionally. It can provide routes and a ground region, but every track crossing that ground region removes copper from the return path. Look at the shortest practical return route for fast edges and switching currents, including connector returns and component decoupling.

The basic construction is one copper-clad laminate with circuitry on both faces. There is no multilayer core-to-core prepreg bond merely because the board has two sides. The planner therefore exposes one substrate dielectric and two copper layers, rather than inventing a four-layer pressing sequence.

A thick two-layer dielectric can require a wide controlled-impedance trace. If the route cannot keep a suitable reference and width, moving to a four-layer build may be more effective than forcing geometry into the available area. Compare board size, routing freedom and assembly effort as well as the bare-board quotation.

2 layer PCB stackup design tool

Select a target thickness, compare construction candidates where available, and inspect the numbered copper layers. You can change every dielectric thickness in the row editor. The finished total includes entered copper and coating allowances. The optional width estimate uses your own approved design Dk; it is an initial single-ended microstrip comparison, not a field-solver or differential-pair result.

2-layer thickness, core and prepreg examples

Start with the mechanical constraint, then check whether the electrical allocation can fit within it. A connector stack height or enclosure is a target; it does not establish the availability of a particular prepreg construction. In a conventional even-layer foil build, cores and bonding gaps can be counted before the exact materials are chosen. Odd-count examples below are geometry allocations only.

Planning examples: 35 碌m finished surface copper, 18 碌m inner copper, zero separate coating allowance. These are reference candidates, not stocked or released constructions. A difference is not an approved tolerance. The tool can change the target and edit every dielectric row. Values above the FR406 reference core range are nominal design targets.

A compact sensor carrier with a two-sided ground strategy

A sensor board can place short signals on the top and retain a broad ground region on the bottom. Check every bottom-side track that cuts that region, including the connections created by connector placement. If the layout depends on a reference beneath fast traces, compare the cost of four layers with the cost of increasing the two-layer board area.

Select the resin system, not just a Tg label

Choose the laminate and bonding system from the electrical path, assembly exposure and reliability requirements. FR-4 describes a family rather than a single dielectric constant. Glass style, resin content, frequency and the measurement method can change the value used in a circuit model. A higher Tg does not automatically mean lower insertion loss, better copper adhesion or a higher continuous service temperature.

For a routine rigid construction, identify the manufacturer and complete grade, approved thickness options and copper foil. For longer high-speed channels, compare the loss model, copper roughness and actual channel length before selecting a low-loss material. A short local bus and a long connector-to-connector route may not need the same material expenditure. Hybrid construction requires a separate bonding and compatibility review.

Keep material substitutions under engineering control. A purchasing description that says only 鈥淔R-4, high Tg鈥� cannot preserve an impedance model or a qualification record. Ask for proposed alternatives before release, compare the required properties, and record the accepted construction in the drawing revision. Supplier data supports selection; it does not certify the finished board or establish current stock.

Use the right thickness in each calculation

Finished board thickness is the sum of the copper, dielectric and any coating allowance defined in the drawing. The dielectric thickness in a microstrip calculation is only the gap between the signal and its reference plane. Entering total board thickness in that calculation can produce an unusable trace width. State whether a supplied core thickness includes copper before adding the copper rows.

The planner counts finished outer copper once and counts each inner copper layer separately. Its candidate search uses symmetric dielectric gaps to expose an initial thickness solution. It does not model resin flow, copper-area fill, glass nesting or pressing shrinkage. After choosing a candidate, replace reference values with the fabricator鈥檚 proposed pressed thicknesses and record the actual laminate and prepreg constructions.

The optional outer-line estimate uses an entered design Dk and a zero-thickness microstrip model. It excludes solder mask, etch shape, roughness and differential coupling. Use it to understand scale, then request the fabricator鈥檚 field-solver table with signal/reference layers, finished copper, line width and pair spacing. An arithmetic thickness match is not an impedance guarantee.

Review the plated interconnect between the two faces

Where signals change faces, define the plated-through connection, finished hole requirement and annular-ring geometry. Distinguish plated and non-plated holes in the drill information. A double-sided board does not need a core-to-core prepreg bond simply because both copper faces are used.

Review how drilling, hole-wall preparation, metallization and outer circuit definition apply to the selected substrate. A low-loss RF laminate and a standard glass-epoxy laminate may need different processing, even when both designs have two copper layers. The real product photograph on this page is an example, not proof that one process recipe applies to every material.

Confirm netlist testing, dimensional checks and any impedance coupon before manufacture. A continuous bottom ground region used as a reference must remain compatible with bottom routing and clearance openings. Bare-board continuity cannot establish that a reference has been preserved for fast signals; that remains a layout and electrical verification task.

Compare complete constructions when reviewing price

Layer count is one cost driver, not a pricing formula. Material consumption, usable panel area, copper, drill families, lamination sequence, surface finish, inspection, electrical test and quantity all contribute. A narrow board can fit a panel efficiently or waste more area after process rails and coupons are included. Small quantities spread setup and fixture costs across fewer boards.

Ask comparable suppliers to quote the same material definition, finished thickness, copper, finish, hole map and acceptance scope. Separate one-time engineering or tooling from repeat fabrication. Also separate bare-board manufacture from component sourcing and assembly. A cheaper quote may simply omit a coupon, a test report or a finish requirement that another quote includes.

The optional budget uses your entered setup, fabrication-per-board and batch test allowances. It has no live factory tariff and makes no claim about current market prices. Its range is an uncalibrated planning scenario, not a statistical confidence interval. Complex and unsupported constructions produce a useful engineering brief instead of a misleading instant price. Contact remains available before any calculation.

Make the first enquiry useful, even with preliminary files

Send the board outline and mechanical requirements, fabrication artwork, drill data, quantity, intended revision and the target thickness. Include the layer order with copper weight or thickness, material grade, core and bonding-layer descriptions. Identify open decisions explicitly. A preliminary design is enough to start a review if it is clearly distinguished from a released manufacturing package.

List controlled-impedance net classes with their signal layer, reference layer, target, tolerance and intended test method. Provide the proposed via spans, finished hole sizes and any backdrill limits. For selective finishes, identify the physical regions and required deposit specification; a broad term such as gold finish does not distinguish wear contacts from solderable pads.

If assembly is included, add the BOM with manufacturer part numbers, placement data, assembly drawing and test expectations. Review connector soldering, thermal exposure and mechanical support where they affect the board. Download the current planner output and attach it with the drawing. The Contact link opens the enquiry page; it does not silently upload files or transfer calculator inputs.

Continue with the decision that remains open

2 layer PCB questions

Engineering references

The linked original documents support material identification and layout principles. Use the current exact-grade and device guidance for a released project. They do not certify a 吃瓜tv production process.