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A useful GaN layout review starts with the exact power device, package and driver architecture, then follows the switching-current and control-return paths through every participating layer. A compact placement is not sufficient evidence of low inductance, clean gate behavior or acceptable isolation. The review must explain which current changes quickly, where its return flows and which physical features keep that loop controlled.

This guide is a release-review method for engineers transferring a GaN power stage from a reference design or first prototype into a manufacturable PCB. It does not provide a universal gate voltage, clearance or layer stack. Those requirements depend on the selected devices and product. Use the power PCB planning page for the wider fabrication scope; the task here is to identify layout changes that require electrical evidence before release.

Trace three loops before judging the board

Identify which GaN architecture you are reviewing

Record the manufacturer, exact ordering code, package revision, datasheet revision, gate-drive circuit and reference-board version. Distinguish a discrete enhancement-mode transistor with an external driver from a device with an integrated driver and protection. A recommendation for one architecture cannot be copied blindly into the other. Similarly, a low-voltage reference layout is not automatically suitable for a higher-voltage product with different insulation and cooling requirements.

Build a change list against the chosen reference: layer spacing, device orientation, bypass-capacitor package, return-plane shape, via positions, heatsink interface and signal routing. Mark every departure rather than writing only 鈥渂ased on vendor evaluation board.鈥� This makes the reference useful as a comparison. The reference-design adaptation checklist addresses the broader transfer to a product; that guide does not replace device-specific requirements.

For an integrated-driver example, the includes local-supply, signal-ground and power-loop guidance specific to that family. For discrete devices, ST’s shows why the drive circuit and parasitic connections must be considered together. Use the current documentation for the part actually fitted. Neither source establishes the ratings or limits of a different GaN component.

Power loop: follow the commutation current

In a half bridge, identify the high-frequency local bypass connection and the two switching devices, then trace the commutation loop that changes current at a transition. The bulk input capacitor may be necessary for energy storage but can be too remote to serve the same high-frequency task. Draw the route through pads, vias, copper regions and capacitor terminations. Include the return layer; two traces that look short in a top-layer screenshot may enclose a substantial loop in the actual stackup.

Label the proposed high-frequency return in the fabrication stackup. If an internal plane immediately beneath the switching components is part of the reference geometry, moving it several dielectric layers away changes the arrangement even if the schematic is identical. The four-layer stackup review provides a place to discuss layer assignments, but a conventional signal-and-ground stackup should not be substituted automatically for a vendor’s power-stage arrangement.

EPC’s illustrates inner-layer return concepts and the need to control common-source and gate-loop inductance. Treat its layouts as device-family guidance rather than a universal footprint. For each candidate, explain the complete loop and verify that the manufacturing files retain the intended dielectric spacing and via connections.

Gate loop: include the return and the local driver supply

For an external gate driver, trace the turn-on and turn-off paths separately when the circuit uses different resistors or diodes. Include the gate pin, source reference, driver output and driver return. A short gate trace with a long or shared return is not a short gate loop. Review the driver’s local supply bypass at the same time; a disturbed supply can make a gate waveform look like a transistor problem when the immediate cause is the driver supply connection.

Use the gate voltage, permitted transient limits, drive impedance and dead-time guidance for the exact transistor and driver combination. Do not transplant a familiar silicon MOSFET drive amplitude or assume negative gate bias is acceptable for every GaN device. The gate waveform must be interpreted at the relevant terminals and against the documented limits. A comfortable waveform measured at a distant driver connector does not establish the voltage at the transistor.

The site’s decoupling placement and return-path guide helps explain why component distance alone is incomplete. Apply that principle to the driver supply, while respecting the selected circuit’s required capacitance and connections. Avoid adding a collection of capacitor values without understanding their installed impedance and the regulator or driver requirements.

Common source: separate signal reference from power-current drop

When power current and gate-return current share source inductance, the changing power current can alter the source voltage seen by the gate loop. A Kelvin source pin or a carefully defined connection can reduce this coupling, but the package and board must both support the chosen arrangement. Do not join the signal return at an arbitrary convenient point on a large copper region and assume all points are equivalent during a fast transition.

A simple sensitivity example explains why small parasitics matter. Assume a current change of 20 A in 5 ns and an effective inductance of 2 nH. The L 脳 di/dt term is 8 V. At an assumed 5 nH it is 20 V. These are educational voltage terms, not predicted drain overshoot or gate excursions. Actual waveforms depend on distributed inductance, capacitance, nonlinear device behavior, damping and the switching trajectory. No board geometry was extracted to obtain these assumed inductances.

Use that calculation to identify the measurement and extraction question, not to approve the layout. A revised arrangement may change several parasitics at once. Likewise, slowing an edge can alter loss and electromagnetic behavior as well as voltage stress. Preserve the before-and-after gate-drive settings and operating conditions when evaluating a physical layout change, otherwise the comparison cannot isolate its effect.

Turn the loop review into a manufacturing and test record

Balance switch-node geometry, cooling and insulation

The switch-node copper is electrically active and may couple displacement current into nearby structures. Increasing its area for thermal reasons can create a different electromagnetic problem. Review the vendor’s thermal path and electrical layout together. Identify which surfaces connect to the switch node, which are accessible to a heatsink and where an insulating interface is required. Do not assume a generic thermal pad or mounting screw arrangement provides the required isolation.

Clearance and creepage come from the applicable product requirements, working voltage, insulation concept, environment and construction, not from a rule based only on the transistor voltage rating. Keep safety boundaries visible across all layers and assembled parts. A copper pour, heatsink fastener or test connector can compromise a boundary that looked acceptable in the schematic. The design’s responsible engineer must establish those requirements before fabrication review.

Extra copper thickness may be useful for current capacity and heat spreading, but it is not a cure for poor loop geometry. Review heavy-copper construction tradeoffs separately from the high-frequency connection. Confirm finished-copper thickness, spacing tolerances, solder-mask openings and the actual component land pattern. The smallest possible component gap is not automatically the best manufacturable or insulated design.

Specify measurements that can distinguish a board issue from a probe artifact

Before energizing a prototype, define the qualified test setup, electrical limits and stop conditions. High-voltage or high-energy switching measurements require appropriate isolation, probe ratings, common-mode performance and laboratory procedures. A grounded oscilloscope clip is not an interchangeable substitute for an appropriately rated measurement connection. Choose the method for the actual node and operating conditions.

Capture the relevant gate and switch-node waveforms with a documented probe arrangement, bandwidth and connection location. Record the bus voltage, load, switching frequency, dead time, drive settings, board temperature and cooling state. Test the important transitions, including startup, shutdown, load changes and the fault behavior specified by the design. A single clean steady-state capture cannot establish behavior across the operating envelope.

When ringing changes after moving the probe, investigate measurement loading and pickup before changing the PCB. Preserve the original trace and setup photograph so another engineer can compare them. If double-pulse testing is used, document the circuit, pulse sequence and its relationship to the intended converter conditions. It is a characterization method for a controlled setup, not an automatic complete product qualification.

Use a short evidence matrix at the release meeting

Give each unresolved item an owner and a disposition: acceptable with evidence, revise and retest, or not yet evaluated. Avoid a single 鈥淒FM passed鈥� label that mixes electrical performance, workmanship and safety. Fabrication review can check defined geometry and construction requirements; it cannot infer the complete converter behavior from Gerber files alone. The evidence matrix makes those boundaries practical rather than burying them in a disclaimer.

Supply the exact stackup, copper specification, board outline, drill information and controlled geometry for PCB manufacturing review. Include the approved BOM, polarity and orientation notes, assembly drawing, programming needs and inspection agreement for board assembly. Flag substitute-sensitive parts such as driver variants, bypass capacitors, gate resistors and current-sense components. Their package and parasitic differences can invalidate a comparison even when nominal values appear equivalent.

End the review with a reproducible revision, not only an attractive layout image. Preserve the reference-board version, deviations, measured operating conditions and open issues alongside the released manufacturing files. To request a construction or assembly quotation, send the GaN board files and unresolved manufacturing questions with quantity and required inspection scope. Attach the evidence matrix manually; the article does not automatically transfer a design or authorize its electrical release.