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Decoupling capacitor placement is a loop problem

A decoupling capacitor helps supply local transient current and control unwanted supply variation. Its PCB layout matters because the electrical path includes the capacitor, device pins, interconnects and return structure. Placing the body close to an IC is useful only when the complete connection supports the intended behavior. Review the loop, the actual component characteristics and the installed power network together.

This page focuses on decoupling capacitor PCB layout, rather than a catalogue of capacitor values. Use the device documentation as the starting requirement and verify the resulting board. The interactive budget below is a simplified educational calculation; it does not simulate a regulator, extract PCB inductance or approve a capacitor selection.

Identify the job of each capacitor

These roles can overlap, but naming the task prevents indiscriminate addition of capacitors. A larger nominal value is not automatically a better high-frequency connection, and a small package is not automatically suitable for voltage, capacitance or assembly requirements. Record the rail, device, intended function and the reason for each important placement decision.

For a broader placement review, use the PCB layout guidelines. For the full project sequence, use the PCB design workflow. This page stays with the power-network geometry and measurements so visitors can investigate decoupling without repeating unrelated manufacturing-file instructions.

Draw the outgoing and return connections

Start at the device supply connection, follow the path to the capacitor and then trace the return to the device reference. Include the pads, vias, planes and any shared narrow conductors. Review the geometry in the actual layer stack. A short top-layer connection can still include a significant transition through a thick board or a detour in the reference copper.

Avoid judging placement solely by straight-line distance between component bodies. Compare electrical connections and the geometry of the loop. A capacitor on the opposite side of the board may have a different connection tradeoff from a top-side capacitor, depending on the package escape and stackup. The correct choice needs the selected device's requirements, physical constraints and verification, not a universal side-of-board rule.

Keep intentional isolation barriers intact. A desire for a shorter high-frequency return does not authorize joining reference regions that must remain isolated. If a signal or power network crosses an isolation boundary, review the complete interface with the responsible engineer and applicable product requirements. Do not add a capacitor between unrelated grounds simply because a generic layout illustration shows a convenient return.

Effective capacitance is a design input

Use the exact capacitor part number and obtain its relevant characteristics at operating conditions. Nominal capacitance and tolerance do not describe every change with DC bias, temperature, aging or frequency. The amount of change depends on the technology and specific part. Keep the source and operating condition with the value used in an analysis instead of applying one generic derating percentage to all capacitors.

Equivalent series resistance and inductance also matter, but they are not the only impedances in the installed path. Pads, vias, planes and device packaging contribute. A component model can help, yet the model's conditions and frequency range need to match the question. Avoid treating a single catalogue ESR value as an accurate description across every frequency and temperature.

For regulator networks, follow the selected device's requirements for capacitance, ESR, topology and placement. Changing an output capacitor can affect stability as well as transient response. A calculation of stored charge does not settle loop stability. Check the relevant application guidance and validate the actual circuit when component substitutions, layout changes or operating conditions differ from the reference design.

Explore a simplified transient voltage budget

Enter a load-current change, an assumed response interval, effective capacitance, ESR, total assumed loop inductance, current-edge time and an allowed voltage deviation. The worksheet calculates separate illustrative terms: capacitive droop 螖I 脳 螖t / C, an ESR step 螖I 脳 ESR and an inductive term L 脳 螖I / 螖t_edge. It also reports the simple target-impedance ratio 螖V_allowed / 螖I.

The displayed sum is an arithmetic comparison of simplified terms. Their peaks need not occur simultaneously, and the sum is neither a simulated waveform nor a rigorous worst-case bound. Regulator response, distributed planes, package behavior, damping and load dynamics are omitted. Entered inductance is an assumption: the tool does not infer it from capacitor distance or automatically extract it from a board.

If the summed terms exceed the entered allowance, the result identifies a budget concern for further investigation. If they are below it, the result still does not establish a passing design. Use the example to understand sensitivity, then replace it with justified inputs. Editing invalidates the previous result and download; contact and manual attachment remain optional next steps.

A numerical example that shows why connections matter

For an illustrative 0.2 A load change lasting 1 碌s, 10 碌F effective capacitance gives a 20 mV capacitive term. With 10 m惟 ESR, the resistive term is 2 mV. If the total assumed loop inductance is 1 nH and the current change occurs over 20 ns, the inductive term is 10 mV. Their arithmetic sum is 32 mV, while a 50 mV allowance divided by 0.2 A gives a 0.25 惟 target-impedance ratio.

This example is not a recommended capacitor network. The 10 碌F value is effective capacitance, and the 1 nH value is an assumed total loop quantity rather than a measured PCB property. Halving the effective capacitance doubles the capacitive term. Increasing the assumed loop inductance doubles the corresponding inductive term when the other inputs remain fixed. These comparisons explain the model without predicting the installed rail waveform.

Use the separate outputs to decide which evidence is missing. If effective capacitance is uncertain, investigate the exact part at bias. If the assumed inductance dominates, review the full connection and an appropriate extraction or measurement. If the load interval is uncertain, characterize the load and supply response. Buying a larger nominal capacitor is not a substitute for resolving those questions.

Avoid turning a collection of capacitors into an unexplained network

Parallel capacitors, plane structures, interconnects and regulator behavior form a frequency-dependent network. Adding different values can introduce interactions as well as reduce impedance in a useful band. Review component models and the installed geometry rather than assuming that more values always produce a better result. Identify the frequency or time-domain requirement that motivates each change.

Ferrite beads and filters also need a defined purpose. Their behavior depends on part characteristics and operating conditions, and they can interact with capacitors and the load. A filter that appears beneficial in one measurement can create another disturbance or affect supply behavior elsewhere. Keep the reference design's assumptions visible, and review any change with the relevant device guidance and system requirements.

Shared connections deserve attention. Several capacitors connected through one narrow path may share an impedance that limits the benefit of adding them. A broad nearby plane is useful only if the device and capacitor can connect to it appropriately. Examine the complete populated design, including escape routing, via clearances and component access, before accepting a schematic network as an adequate physical implementation.

Measure at a meaningful location with a controlled setup

Define the rail, device location, load event and operating condition before probing. Record the probe arrangement, bandwidth and return connection. A long probe ground lead can introduce artifacts that resemble the disturbance being investigated. Compare measurements with consistent setups and distinguish actual rail behavior from instrument loading or pickup. The test record should let another engineer reproduce the observation.

Measure under the relevant firmware state, active interfaces, input supply and enclosure condition. Startup, load transitions and steady operation can expose different behavior. If an issue is intermittent, correlate it with the event rather than averaging it away. Include the exact board revision and fitted capacitor parts so the result remains traceable when the design or BOM changes.

An illustrative review might compare two layout variants while keeping the components, firmware and test setup controlled. The purpose is to isolate the effect of the connection change. This page does not present measured variant data or a customer success story; the diagrams explain what to compare, while the actual product evidence must come from its own analysis and tests.

Carry the decoupling decision into manufacturing

Specify the exact approved component and permitted alternatives. Keep polarity, orientation, voltage rating and population variants clear where relevant. If a capacitor is close to a package for an electrical reason, identify any assembly or rework constraints before release. The design-for-assembly page helps review that physical access without substituting assembly convenience for the electrical requirement.

When the board changes, revisit the affected loop and the evidence supporting it. A moved via, a changed reference layer or a component substitution can alter the installed behavior even if the schematic connectivity is unchanged. Record what must be retested and which assumptions remain valid. For unexplained symptoms, the PCB design mistakes guide offers a structured investigation record.

Decoupling layout questions

Primary references for deeper investigation

discusses decoupling and nonideal capacitor behavior. provides background on physical interconnections. Use those references with the exact device and capacitor documentation; the original worksheet and examples here deliberately separate educational arithmetic from an installed-system prediction.