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A net name identifies an intended electrical group in the design database. Names such as GND, a supply rail or a signal label are useful to people and design tools, but spelling alone is not physical connectivity. The schematic must contain the intended connections, and the PCB must implement them. Two copper features that look close in a screenshot may still be electrically separate.

Conversely, a net does not need to be drawn as one continuous track on one layer. Pads, vias, tracks on different layers and filled copper zones can form a single implemented connection. A via can move the route between layers without changing the net. The physical route and the logical net are different representations of the same connectivity task.

A component normally connects nets through its electrical behavior rather than simply merging every terminal into one net. A resistor, capacitor or transistor belongs to the circuit between specified nodes. Special intentional connections, such as a net tie, need an explicit design representation and review. Do not use arbitrary copper shorts as a substitute for documenting an intentional relationship.

Schematic editors use label scope to determine where named connections apply. In KiCad, local, global and hierarchical labels have different roles. A repeated text label on separate sheets may not mean what an engineer expects if the label type or hierarchy is wrong. Check the editor鈥檚 connectivity model rather than assuming that visible text anywhere in the project joins the same net.

Hierarchical designs also need consistent sheet pins and labels across the sheet boundary. A signal can appear correctly named inside a subcircuit while failing to connect at the parent level. When investigating a missing connection, follow the actual signal through the hierarchy, including the interface pins, instead of searching only for matching text.

Names should be understandable and consistent with the design鈥檚 conventions. Restrictions and escaping rules vary by tool and format, so there is no universal list of prohibited characters that covers every workflow. Use the documentation for the actual EDA version and the downstream exchange format. If an export renames a signal, preserve the mapping needed for manufacturing and test.

A bus groups related signals for organization and schematic expression; it does not mean those signals are electrically shorted together. For example, a collection of data lines still contains distinct nets. Check how the EDA system expands bus members and connects them to individual pins. A visually tidy bus drawing can conceal a naming or membership error if the underlying connection is wrong.

A net class groups nets for design rules such as routing width or clearance. Assigning two nets to the same class does not electrically connect them. Similarly, differential-pair naming or rule assignment establishes a routing relationship, not a direct copper connection between the pair. The electrical circuit and the applicable constraints must both be represented correctly.

A netlist is a representation of connectivity for a particular exchange or checking task. File formats and their supported information vary. Use the PCB netlist guide when the question is a file handoff, export or comparison. This page focuses on what the connections mean and how to recognize a mismatch between intended and implemented connectivity.

Start with a consistent project revision and update the PCB from the intended schematic state. Review the changes rather than accepting a large update without inspection. Pay attention to removed or renamed references, footprint changes and pad-number mappings. A correct net name connected to the wrong footprint pad can still produce the wrong physical circuit.

Unrouted connection indicators are helpful guides, but they are not manufacturing copper. A line between two pads on the screen can indicate an intended connection that has not yet been routed. Filled zones also need attention: thermal reliefs, clearances, islands and zone settings can change which pads are actually connected. Refill and rerun the appropriate checks after relevant edits.

For the CAD handoff workflow, the KiCad schematic-to-PCB guide covers the adjacent task. Keep both the schematic and board under the same revision discipline. A file exported from a previous state may be internally consistent yet fail to represent the design that was actually approved for production.

An open interrupts a required connection. In a simplified connectivity graph, terminals that should belong to one connected group become separated. The physical cause could be an unrouted segment, a missing via connection, an isolated zone or a manufacturing defect. Diagnosing the cause requires more information than simply knowing that continuity is absent.

A short joins groups that should remain separate. In a graph, an extra connection can merge two intended nets. This can occur through an unintended track, incorrect copper fill, wrong footprint mapping or a fabrication or assembly defect. A design short and a manufacturing short need different corrective actions, even when an electrical test reports a similar symptom.

The interactive lab uses a small fixed example with two intended nets. You can remove a required connection or add a bridge between the groups, then inspect the computed connected components. The result reports the mismatch in plain language. It does not load your CAD file, simulate components or validate a production board. Its value is making the connectivity concept visible and testable.

Suppose a prototype input is stuck at the same level as a supply rail. First establish the expected schematic connection and component behavior. Identify the relevant references and pins, then compare the board database and released manufacturing outputs. Do not assume an electrical symptom proves that two nets are directly shorted; component faults or circuit conditions can create similar observations.

If inspection finds unexpected copper between the groups, determine whether it exists in the released design or only in the physical sample. A design correction belongs in the controlled source files and their regenerated outputs. A manufacturing or assembly discrepancy needs traceable sample information and the agreed inspection or test process. Preserve the evidence before attempting a repair that could obscure the original condition.

For an open, follow the intended path systematically. Include layer transitions, plated connections and zone membership. A track that visually reaches a pad may have a clearance or mapping issue in the database. Use the EDA checks and the applicable electrical test procedure together, while keeping the design review and physical test results distinguishable.

Electrical rule checking in the schematic can identify certain inconsistencies in pin connections and defined rules. Design rule checking in layout can identify certain geometric and connectivity problems. Both depend on the configured rules, library data and current project state. A clean report is useful evidence, but it is not proof that the product implements the intended function correctly.

Bare-board electrical testing checks a physical board against a specified connectivity reference and test method. It does not validate the component selection or the assembled product鈥檚 complete function. Assembly testing introduces additional requirements because components and their behavior are now part of the circuit. Choose the method according to the question being asked.

The PCB electrical testing page explains the manufacturing test context, while PCB DFM addresses the consistency and manufacturability of the release package. Provide the appropriate reference data and acceptance requirements. Avoid treating an exported netlist, a DRC screenshot and a functional test report as interchangeable proof.

State the board revision, component references and pin or pad numbers involved. Include the expected net names and describe whether the issue appears in CAD, fabrication outputs, a bare board or an assembled sample. This distinction helps route the enquiry to the right review. A screenshot should include the layer, orientation and relevant location rather than only a cropped colored line.

Provide the approved manufacturing data and any agreed independent connectivity reference. Explain which files are authoritative and whether a design revision has occurred since the last build. If a special intentional connection exists, such as a net tie or test configuration, document it explicitly. Otherwise a reviewer may correctly identify a difference but lack the circuit context needed to interpret it.

Use the lab鈥檚 downloadable explanation as a teaching note only. It contains the public example鈥檚 connections, not information extracted from your project. Your own circuit files should be shared through the appropriate project channel when a real review is requested. The tool does not submit files, send enquiries or add your project data to analytics.

Connectivity comparison is useful only when its reference is understood. A reference generated from the same already-incorrect output may reproduce the error rather than reveal it. Decide which design state is authoritative and how the comparison data was produced. Keep that provenance with the released files so that a later investigation can distinguish a design mismatch from a data-processing discrepancy.

When a project moves between EDA systems or manufacturing representations, confirm that component references and pin numbers remain interpretable. Net names may be changed or normalized during exchange, while the underlying terminal connectivity should remain consistent with the intended design. A name difference by itself is not always an electrical difference; an identical name is not always proof of a correct pad map.

For an engineering change, identify the intentional differences before comparing revisions. A removed option resistor, a changed connector pinout or a revised net tie may produce a legitimate connectivity change. Document that change rather than suppressing every reported difference. The useful result is a reviewed explanation of each relevant discrepancy, not merely a clean-looking report.

The lab on this page makes the distinction visible using only four terminals. Removing J1鈥揜1 creates an open within intended Net A; adding R1鈥揜2 joins intended Nets A and B. If both actions are selected, both problems remain relevant. A single summary such as 鈥渃ontinuity found鈥� would hide the missing required connection. That is why the result shows connected groups, a cross-net short and missing required links separately.

A real board contains many more connections, component behaviors and manufacturing constraints than this example. Use appropriate CAD and test tools for the actual design, and retain the report conditions and revisions. The small model is a learning aid that helps a visitor ask a more precise engineering question, not a replacement for those tools.

Does changing a net鈥檚 color change connectivity? No. Display color is an aid to reading the design. Connectivity is established by the project鈥檚 electrical model and its physical implementation, not by matching colors on the screen.

Can two nets have similar names? They can be distinct despite similar spelling, and hierarchical scope can affect how names are resolved. Verify the actual connection and tool conventions rather than relying on a visual name comparison alone.

Does a ground plane connect every ground pad automatically? Only when the zone, clearances, thermal connections and other settings result in a physical connection. Check the filled result and the relevant rules after changes.

Can a continuity meter replace design review? It can observe an electrical condition under a defined procedure, but components, stored charge and parallel paths affect interpretation. The measurement does not tell you whether the intended design was correct. Reconcile the circuit intent, released files and physical evidence before drawing that conclusion.