HDI engineering
HDI Stackup & Sequential Lamination: 1+N+1, 2+N+2 & Via Spans
An HDI stackup describes copper, dielectric layers and their interconnects. Sequential lamination adds and processes build-up layers in stages. Select the structure from routing needs and a reviewed fabrication sequence, not total layer count alone.
The practical decision
Notation such as 1+N+1 or 2+N+2 describes build-up layers around an inner N-layer structure. It does not define every via, material, drill operation or qualified lamination schedule. Supply the full layer map and via spans.
- Routing needWhich layers must connect?
- Layer mapCopper + dielectric + spans
- Process proposalBuild-up + drill + fill
- Release reviewElectrical + thermal + test
Read the notation without over-interpreting it
| Notation | Concept | Not settled by the name |
|---|---|---|
| 1+N+1 | One build-up layer on each side | Materials, geometry, buried vias or acceptance |
| 2+N+2 | Two build-up layers on each side | Stacked/staggered vias and complete sequence |
| 3+N+3 | Three build-up layers on each side | Suitability or necessity for the application |
| Any-layer / ELIC | Dense architecture with extensive layer connectivity | Approval of arbitrary stacked structures or rules |
Read the notation without assuming the missing details
In the common symmetric notation 1+N+1, one build-up layer is described on each side of an N-layer central structure. In 2+N+2, two are described on each side. The notation helps discuss architecture, but the drawing must still identify the conductive layers, dielectric structures and via connections. A six-layer example can be written 1+4+1; an eight-layer example can be 2+4+2. These arithmetic descriptions do not establish that either structure meets a particular package escape or process requirement.
The central structure may itself contain buried connections or subassemblies. Two designs with the same notation can therefore have different manufacturing steps and costs. Likewise, the number of build-up layers should not be used as a universal count of every pressing operation in the factory. Ask for the proposed sequence and identify which steps form the critical interconnections. Terminology such as sub-lamination and sequential lamination can describe different aspects of that sequence.
Do not assign a standards construction type solely from the shorthand. The is a starting point for checking document status; the invoked project specification and licensed standard determine the applicable requirements. The useful design output is a labelled stackup, not a claim that a shorthand certifies it. The HDI manufacturing hub provides the broader service context. Record layer access and sequence so the reviewer can identify the required construction and its purpose. If the central stack is still undecided, mark N as unresolved rather than treating the notation as a finished manufacturing specification.
Illustrative 1+4+1 layer map
A six-copper-layer concept comprises outer L1, inner L2鈥揕5 and outer L6. One possible via description includes L1鈥揕2 and L6鈥揕5 microvias. Specify each surface-to-inner blind span and each buried-via subassembly pair separately. If the connection strategy is still open, compare blind and buried via routes by the required physical access. This example explains communication, not a qualified material or dimensional construction.
| Part | Show in drawing | Open engineering decision |
|---|---|---|
| L1 to L2 | Top build-up dielectric, copper and microvia | Depth, opening and target geometry |
| L2 to L5 | Inner layers and any internal interconnect | Buried-via need and process sequence |
| L6 to L5 | Bottom build-up and via relationship | Symmetry or justified different construction |
| Complete PCB | All via types, impedance and thickness | Compatibility and verification of the full stack |
Draw the via spans before routing the entire board
Create a via-span table with a unique identifier, start layer, end layer, intended formation route, fill or cap requirements and the regions or nets that use it. Show the same identifiers on a cross-section. A CAD via definition that connects two layers electrically does not by itself establish that the proposed manufacturing sequence can create it. Check accessibility at the stage when the hole is formed.
For a conceptual 1+4+1 example, label the final layers L1 through L6. The central structure is L2 through L5, with outer build-up layers L1 and L6. Candidate connections might include L1-L2 and L6-L5 microvias, plus a central connection formed before the outer layers are added. This is an explanatory map, not a recommended universal stack. The actual diameter, depth, land geometry and material set need separate review.
For a conceptual 2+4+2 structure, the central layers become L3 through L6 in an eight-layer board. Connections from L1 to L2 and L2 to L3 can be arranged with different lateral relationships. A stacked route and a staggered route create different geometry and interfaces even though both reach the central stack. Avoid describing them as interchangeable symbols. Identify the space available for the capture lands and connecting traces, and relate that space to the actual package escape. The microvia geometry review supports the individual hole dimensions. Keeping spans explicit early can prevent a completed layout from depending on a connection that requires an unplanned process or a qualification scope the project has not accepted.
The manufacturing sequence matters
Use the HDI cost comparison worksheet to separate the commercial effects of alternative structures.
Make the manufacturing sequence visible
A sequence diagram should show the central construction, each added dielectric and copper stage, hole formation, metallization and any fill or planarization needed before the next stage. The precise route belongs to the fabricator, but the designer needs enough visibility to understand which interfaces are being created. Do not assume that a generic 鈥渟equential lamination鈥� label means only one drilling method or one universal set of operations.
At each stage, ask which surfaces are accessible. A connection that becomes buried must be completed while its relevant surfaces are available. If a later microvia lands on a previously formed feature, identify that interface and the required surface condition. The operation history matters because the final cross-section alone may not reveal how a target was prepared or how many thermal processes it experienced.
Also identify points where a proposed design change becomes expensive or irreversible for the order. Changing an outer trace before imaging is different from changing an internal connection after a substructure has been built. This does not mean the customer must control the factory's detailed process recipe. It means the released construction and the supplier's proposed route should agree. The worksheet can record a stage name, the layers present, holes formed and evidence or inspection associated with that stage. If the supplier proposes an alternative route, review whether it preserves the electrical geometry, materials and qualification basis. A lower-cost sequence can be valuable, but it should be an explicit engineering alternative rather than an invisible substitution inferred from the same final layer count.
Review electrical and process requirements together
Identify the routing bottleneck that requires each interconnect. Consider impedance references, dielectric thickness and copper at the same time as via structure. Include assembly thermal exposure and rework expectations. If quoting changes the stack, recheck the affected geometry and electrical constraints before releasing files.
| Question | Required input |
|---|---|
| Does every via have a span? | Layer-pair table aligned to drill data |
| Is every build-up level needed? | Escape/routing constraint and alternatives |
| Are material dimensions consistent? | Stack drawing, tolerances and impedance intent |
| How is the chain verified? | Agreed construction, electrical and reliability evidence |
Submit the proposed construction for HDI manufacturing review before freezing unsupported rules into the layout.
Compare routing relief with the added construction burden
The reason for additional build-up is usually a routing or interconnection requirement. Identify the bottleneck: package pitch, number of escape rows, available trace geometry, reference continuity or transition count. Do not add another build-up level merely because it is available. Conversely, reducing the number of build-up levels can make routing impractical or force an undesirable signal path. The comparison should use a representative escape region, not only total board area.
Consider two candidate layouts for the same device. One uses fewer build-up levels but additional conventional routing layers; the other uses another build-up level to reach routing channels sooner. Compare the actual escape geometry, total thickness, reference arrangement, via interfaces and process proposal. There is no universal rule that fewer total layers is cheaper or that fewer lamination stages always wins. Materials, feature sizes, yield assumptions and test scope can change the result.
For high-speed signals, include the complete transition and return path in the comparison. A shorter via connection is not automatically a good channel if nearby reference continuity is poor. If a conventional through connection leaves a significant unused section, backdrilling may be one alternative to review, not an automatic replacement for HDI. A useful trade study records what each route solves and what new constraint it introduces. This keeps the design from optimizing a single metric while making assembly, thickness or qualification harder. Use actual supplier feedback for manufacturability and cost; do not infer a price multiplier from notation alone.
Match reliability evidence to the chosen interfaces
Qualification evidence should describe a construction that is relevant to the proposed board. Identify whether the test structure represents the same microvia stacking arrangement, dielectric system, hole geometry and manufacturing sequence. A report for a different interface may provide background information without qualifying the new route. Ask the supplier to state the similarities and differences rather than presenting a generic certificate as a complete answer.
Separate fabrication acceptance from product qualification. A bare-board electrical test establishes a particular set of continuity and isolation observations; it does not establish performance through every assembly thermal exposure or service condition. Coupon design, conditioning, thermal history and electrical monitoring should be agreed where they are required. Use the microvia evidence review to define the questions without declaring all stacked constructions unacceptable.
Keep the test basis linked to the released sequence. If a supplier changes a fill process, material or stage relationship, evaluate whether the existing evidence still represents the construction. The answer may be that no additional testing is needed, that a limited comparison is enough, or that new qualification is required. It should be documented rather than assumed. For development boards, distinguish exploratory samples from qualification specimens and record which revision was tested. A clear evidence map makes risk visible without turning the webpage into an unsupported acceptance standard. It also helps procurement compare offers that use different constructions under the same 鈥�2+N+2鈥� label. The label is a starting description; the interfaces and evidence determine what the team is actually buying.
Working document
Prepare your handoff checklist
Open the editable text worksheet, save a copy and record the requirement, owner and evidence for each item. Keep unanswered points visible when requesting review.
- Copper numbering and total count
- Build-up notation and cross-section
- Via pairs and stacked/staggered relationships
- Inner structure and buried vias
- Materials, copper/dielectric thickness and tolerances
- Impedance targets and reference layers
- Fabricator-proposed process sequence
- Assembly thermal exposure and verification
- Approved stack linked to drill/fabrication revisions
The Contact page is a separate enquiry step. Attach your completed worksheet and relevant files there using its available submission options; this page does not automatically transfer your answers.
Release the layer map and quote the actual build
The release package should include the final layer table, via-span table, cross-section, material proposal, impedance requirements and any critical regional restrictions. Add the supplier-agreed operation sequence at the level needed to identify the construction. Keep detailed proprietary process parameters separate from the customer-facing requirement; the purpose is to avoid ambiguity, not to dictate an unverified recipe.
For a quotation, supply prototype and production quantities, target thickness, package information and the required evidence. If several architectures remain possible, identify the fixed constraints and ask for alternatives against them. A quote based only on layer count and board dimensions cannot reliably compare different HDI routes. Record one-time engineering and qualification separately from recurring fabrication where the supplier can provide that distinction.
Before authorizing manufacture, inspect the exported drill and copper information against the approved table. Ensure the CAD names and the final layer names agree. Resolve every via group whose start or end layer changed during stackup development. Send the complete scope through PCB manufacturing review, retaining the HDI-specific construction record. The useful result is a build that can be described, quoted and checked consistently. A designer should be able to point to a connection and explain when it is formed, which layers it reaches and what evidence supports it. That is a stronger basis for release than a visually impressive stackup image or a shorthand that leaves the important interfaces unstated.
Questions before you release the files
Does 2+N+2 mean two total press operations?
Not necessarily. It describes build-up architecture. Confirm the complete sequence for the inner structure and all operations.
Can equal layer counts have different HDI costs?
Yes. Via relationships, processing, materials, panel use and verification can differ.
Should every dense BGA use any-layer HDI?
No. Compare constructions against the actual escape and routing requirement. Complexity should solve a defined problem and have process support.
Continue with the next engineering task
Technical references
2019 reliability background on latent microvia-interface failures. It is not a substitute for the current agreed performance specification.